From patchwork Thu Jan 26 16:22:01 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 137967 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 49212B6F9D for ; Fri, 27 Jan 2012 03:22:50 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753095Ab2AZQW3 (ORCPT ); Thu, 26 Jan 2012 11:22:29 -0500 Received: from hqemgate03.nvidia.com ([216.228.121.140]:1500 "EHLO hqemgate03.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753092Ab2AZQW2 (ORCPT ); Thu, 26 Jan 2012 11:22:28 -0500 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate03.nvidia.com id ; Thu, 26 Jan 2012 08:36:36 -0800 Received: from hqnvemgw02.nvidia.com ([172.17.108.22]) by hqnvupgp07.nvidia.com (PGP Universal service); Thu, 26 Jan 2012 08:22:27 -0800 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Thu, 26 Jan 2012 08:22:27 -0800 Received: from thelma.nvidia.com (Not Verified[172.16.212.77]) by hqnvemgw02.nvidia.com with MailMarshal (v6, 7, 2, 8378) id ; Thu, 26 Jan 2012 08:22:27 -0800 Received: from tbergstrom-lnx.Nvidia.com (dhcp-10-21-25-176.nvidia.com [10.21.25.176]) by thelma.nvidia.com (8.13.8+Sun/8.8.8) with ESMTP id q0QGMKFr011131; Thu, 26 Jan 2012 08:22:25 -0800 (PST) From: Peter De Schrijver To: Peter De Schrijver Cc: Colin Cross , Olof Johansson , Stephen Warren , Russell King , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v1 1/3] ARM: tegra: definitions for flow controller Date: Thu, 26 Jan 2012 18:22:01 +0200 Message-Id: <1327594923-21822-2-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.7.7.rc0.72.g4b5ea.dirty In-Reply-To: <1327594923-21822-1-git-send-email-pdeschrijver@nvidia.com> References: <1327594923-21822-1-git-send-email-pdeschrijver@nvidia.com> X-NVConfidentiality: public Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Introduce some definitions for the tegra flow contoller. This will be used by the code which controls entering and leaving LP3. Signed-off-by: Peter De Schrijver --- arch/arm/mach-tegra/flowctrl.h | 37 +++++++++++++++++++++++++++++++++++++ 1 files changed, 37 insertions(+), 0 deletions(-) create mode 100644 arch/arm/mach-tegra/flowctrl.h diff --git a/arch/arm/mach-tegra/flowctrl.h b/arch/arm/mach-tegra/flowctrl.h new file mode 100644 index 0000000..74c6efb --- /dev/null +++ b/arch/arm/mach-tegra/flowctrl.h @@ -0,0 +1,37 @@ +/* + * arch/arm/mach-tegra/flowctrl.h + * + * functions and macros to control the flowcontroller + * + * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see . + */ + +#ifndef __MACH_TEGRA_FLOWCTRL_H +#define __MACH_TEGRA_FLOWCTRL_H + +#define FLOW_CTRL_HALT_CPU0_EVENTS 0x0 +#define FLOW_CTRL_WAITEVENT (2 << 29) +#define FLOW_CTRL_WAIT_FOR_INTERRUPT (4 << 29) +#define FLOW_CTRL_JTAG_RESUME (1 << 28) +#define FLOW_CTRL_HALT_CPU_IRQ (1 << 10) +#define FLOW_CTRL_HALT_CPU_FIQ (1 << 8) +#define FLOW_CTRL_CPU0_CSR 0x8 +#define FLOW_CTRL_CSR_INTR_FLAG (1 << 15) +#define FLOW_CTRL_CSR_EVENT_FLAG (1 << 14) +#define FLOW_CTRL_CSR_ENABLE (1 << 0) +#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14 +#define FLOW_CTRL_CPU1_CSR 0x18 + +#endif