From patchwork Wed Dec 14 11:39:40 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Martin X-Patchwork-Id: 131349 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 38B361007D5 for ; Wed, 14 Dec 2011 22:40:06 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756944Ab1LNLkF (ORCPT ); Wed, 14 Dec 2011 06:40:05 -0500 Received: from mail-ee0-f46.google.com ([74.125.83.46]:45549 "EHLO mail-ee0-f46.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756276Ab1LNLkC (ORCPT ); Wed, 14 Dec 2011 06:40:02 -0500 Received: by eekc4 with SMTP id c4so663631eek.19 for ; Wed, 14 Dec 2011 03:40:00 -0800 (PST) Received: by 10.180.4.42 with SMTP id h10mr3857211wih.22.1323862800855; Wed, 14 Dec 2011 03:40:00 -0800 (PST) Received: from e103592.peterhouse.linaro.org (fw-lnat.cambridge.arm.com. [217.140.96.63]) by mx.google.com with ESMTPS id k5sm3012382wiz.9.2011.12.14.03.39.58 (version=SSLv3 cipher=OTHER); Wed, 14 Dec 2011 03:40:00 -0800 (PST) From: Dave Martin To: linux-arm-kernel@lists.infradead.org Cc: patches@linaro.org, Anton Vorontsov , Barry Song , Catalin Marinas , Colin Cross , Haojian Zhuang , John Linn , Kukjin Kim , Linus Walleij , linux-omap@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-sh@vger.kernel.org, linux-tegra@vger.kernel.org, Magnus Damm , Paul Mundt , Pawel Moll , Rob Herring , Sascha Hauer , Shawn Guo , Tony Lindgren , Will Deacon Subject: [PATCH v4 REPOST 4/5] highbank: Unconditionally require l2x0 L2 cache controller support Date: Wed, 14 Dec 2011 11:39:40 +0000 Message-Id: <1323862781-3465-5-git-send-email-dave.martin@linaro.org> X-Mailer: git-send-email 1.7.4.1 In-Reply-To: <1323862781-3465-1-git-send-email-dave.martin@linaro.org> References: <1323862781-3465-1-git-send-email-dave.martin@linaro.org> Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org If running in the Normal World on a TrustZone-enabled SoC, Linux does not have complete control over the L2 cache controller configuration. The kernel cannot work reliably on such platforms without the l2x0 cache support code built in. This patch unconditionally enables l2x0 support for the Highbank SoC. Thanks to Rob Herring for this suggestion. [1] Signed-off-by: Dave Martin [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2011-November/074495.html Acked-by: Rob Herring --- arch/arm/Kconfig | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d33eb39..744296d 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -340,12 +340,12 @@ config ARCH_HIGHBANK select ARM_AMBA select ARM_GIC select ARM_TIMER_SP804 + select CACHE_L2X0 select CLKDEV_LOOKUP select CPU_V7 select GENERIC_CLOCKEVENTS select HAVE_ARM_SCU select HAVE_SMP - select MIGHT_HAVE_CACHE_L2X0 select USE_OF help Support for the Calxeda Highbank SoC based boards.