Show patches with: Series = [v1] clk: tegra20: Add 216 MHz entry for PLL_X       |    State = Action Required       |    Archived = No       |   2 patches
Patch Series A/F/R/T S/W/F Date Submitter Delegate State
[v1,2/2] clk: tegra20: Correct PLL_C_OUT1 setup [v1] clk: tegra20: Add 216 MHz entry for PLL_X 1 - - - 0 0 0 2017-12-11 Dmitry Osipenko New
[v1] clk: tegra20: Add 216 MHz entry for PLL_X [v1] clk: tegra20: Add 216 MHz entry for PLL_X - - - - 0 0 0 2017-12-11 Dmitry Osipenko New