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[v1,0/5] NVIDIA Tegra AHB DMA controller driver

Message ID cover.1506380746.git.digetx@gmail.com
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Series NVIDIA Tegra AHB DMA controller driver | expand

Message

Dmitry Osipenko Sept. 25, 2017, 11:22 p.m. UTC 
NVIDIA Tegra20/30 SoC's have AHB DMA controller. It has 4 DMA channels,
supports AHB <-> Memory and Memory <-> Memory transfers, slave / master
modes. This driver is primarily supposed to be used by gpu/host1x in a
master mode, performing 3D HW context stores.

Dmitry Osipenko (5):
  clk: tegra: Add AHB DMA clock entry
  clk: tegra: Bump SCLK clock rate to 216MHz on Tegra20
  dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller
  dmaengine: Add driver for NVIDIA Tegra AHB DMA controller
  ARM: dts: tegra: Add AHB DMA controller nodes

 .../bindings/dma/nvidia,tegra20-ahbdma.txt         |  23 +
 arch/arm/boot/dts/tegra20.dtsi                     |   9 +
 arch/arm/boot/dts/tegra30.dtsi                     |   9 +
 drivers/clk/tegra/clk-id.h                         |   1 +
 drivers/clk/tegra/clk-tegra-periph.c               |   1 +
 drivers/clk/tegra/clk-tegra20.c                    |   8 +-
 drivers/clk/tegra/clk-tegra30.c                    |   2 +
 drivers/dma/Kconfig                                |   9 +
 drivers/dma/Makefile                               |   1 +
 drivers/dma/tegra20-ahb-dma.c                      | 679 +++++++++++++++++++++
 10 files changed, 741 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/dma/nvidia,tegra20-ahbdma.txt
 create mode 100644 drivers/dma/tegra20-ahb-dma.c

Comments

Vinod Koul Sept. 28, 2017, 9:31 a.m. UTC | #1 
On Tue, Sep 26, 2017 at 02:22:01AM +0300, Dmitry Osipenko wrote:
> NVIDIA Tegra20/30 SoC's have AHB DMA controller. It has 4 DMA channels,
> supports AHB <-> Memory and Memory <-> Memory transfers, slave / master
> modes. This driver is primarily supposed to be used by gpu/host1x in a
> master mode, performing 3D HW context stores.
> 
> Dmitry Osipenko (5):
>   clk: tegra: Add AHB DMA clock entry
>   clk: tegra: Bump SCLK clock rate to 216MHz on Tegra20
>   dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller
>   dmaengine: Add driver for NVIDIA Tegra AHB DMA controller
>   ARM: dts: tegra: Add AHB DMA controller nodes

I don't think they are dependent, so consider sending them separately
Dmitry Osipenko Sept. 28, 2017, 12:24 p.m. UTC | #2 
On 28.09.2017 12:31, Vinod Koul wrote:
> On Tue, Sep 26, 2017 at 02:22:01AM +0300, Dmitry Osipenko wrote:
>> NVIDIA Tegra20/30 SoC's have AHB DMA controller. It has 4 DMA channels,
>> supports AHB <-> Memory and Memory <-> Memory transfers, slave / master
>> modes. This driver is primarily supposed to be used by gpu/host1x in a
>> master mode, performing 3D HW context stores.
>>
>> Dmitry Osipenko (5):
>>   clk: tegra: Add AHB DMA clock entry
>>   clk: tegra: Bump SCLK clock rate to 216MHz on Tegra20
>>   dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller
>>   dmaengine: Add driver for NVIDIA Tegra AHB DMA controller
>>   ARM: dts: tegra: Add AHB DMA controller nodes
> 
> I don't think they are dependent, so consider sending them separately
> 

Well, they are dependent in a sense of making driver usable. Only the "SCLK rate
bump" patch isn't strictly needed.

Splitting this series won't cause building failures, but all pieces should be in
place for the working driver. So I suppose it is okay if clk patches would get
in earlier than the others, I'll split the series.

Thank you for the review.