[v2,0/6] firmware: tegra: Add MRQ support for Tegra264.

Message ID	20230510113129.4167493-1-pdeschrijver@nvidia.com
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Series	firmware: tegra: Add MRQ support for Tegra264. \| expand [v2,0/6] firmware: tegra: Add MRQ support for Tegra264. [v2,1/6] dt-bindings: mailbox: tegra: Document Tegra264 HSP [v2,2/6] mailbox: tegra: add support for Tegra264 [v2,3/6] soc: tegra: fuse: add support for Tegra264 [v2,4/6] dt-bindings: Add bindings to support DRAM MRQ GSCs [v2,5/6] dt-bindings: memory-region property for tegra186-bpmp [v2,6/6] firmware: tegra: bpmp: Add support for DRAM MRQ GSCs

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From: Peter De Schrijver <pdeschrijver@nvidia.com>
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Subject: [PATCH v2 0/6] firmware: tegra: Add MRQ support for Tegra264.
Date: Wed, 10 May 2023 14:31:24 +0300
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Series

firmware: tegra: Add MRQ support for Tegra264. | expand

Message

Peter De Schrijver May 10, 2023, 11:31 a.m. UTC

In Tegra264 the carveouts (GSCs) used to communicate between BPMP and
CPU-NS may reside in DRAM. The location will be signalled using reserved
memory node in DT. Additionally some minor updates to the HSP driver are
done to support the new chip.

Peter De Schrijver (4):
  dt-bindings: mailbox: tegra: Document Tegra264 HSP
  dt-bindings: Add bindings to support DRAM MRQ GSCs
  dt-bindings: memory-region property for tegra186-bpmp
  firmware: tegra: bpmp: Add support for DRAM MRQ GSCs

Stefan Kristiansson (2):
  mailbox: tegra: add support for Tegra264
  soc: tegra: fuse: add support for Tegra264

 .../firmware/nvidia,tegra186-bpmp.yaml        |  37 ++-
 .../bindings/mailbox/nvidia,tegra186-hsp.yaml |   1 +
 .../nvidia,tegra264-bpmp-shmem.yaml           |  45 ++++
 drivers/firmware/tegra/bpmp-tegra186.c        | 214 ++++++++++++------
 drivers/firmware/tegra/bpmp.c                 |   4 +-
 drivers/mailbox/tegra-hsp.c                   |  16 +-
 drivers/soc/tegra/fuse/tegra-apbmisc.c        |   3 +-
 include/soc/tegra/fuse.h                      |   3 +-
 8 files changed, 251 insertions(+), 72 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml

Comments

Peter De Schrijver May 10, 2023, 11:44 a.m. UTC | #1

On Wed, May 10, 2023 at 02:31:24PM +0300, Peter De Schrijver wrote:
> In Tegra264 the carveouts (GSCs) used to communicate between BPMP and
> CPU-NS may reside in DRAM. The location will be signalled using reserved
> memory node in DT. Additionally some minor updates to the HSP driver are
> done to support the new chip.
> 
> Peter De Schrijver (4):
>   dt-bindings: mailbox: tegra: Document Tegra264 HSP
>   dt-bindings: Add bindings to support DRAM MRQ GSCs
>   dt-bindings: memory-region property for tegra186-bpmp
>   firmware: tegra: bpmp: Add support for DRAM MRQ GSCs
> 
> Stefan Kristiansson (2):
>   mailbox: tegra: add support for Tegra264
>   soc: tegra: fuse: add support for Tegra264

Changes in v2:

- Added signoff messages
- Updated bindings to support DRAM MRQ GSCs
- Split out memory-region property for tegra186-bpmp
- Addressed sparse errors in bpmp-tegra186.c