From patchwork Thu Dec 13 09:34:17 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joseph Lo X-Patchwork-Id: 1012695 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="Ii4peS6+"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 43FpRw6GTLz9s1c for ; Thu, 13 Dec 2018 20:34:52 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727254AbeLMJev (ORCPT ); Thu, 13 Dec 2018 04:34:51 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:1317 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727063AbeLMJev (ORCPT ); Thu, 13 Dec 2018 04:34:51 -0500 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Thu, 13 Dec 2018 01:34:46 -0800 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Thu, 13 Dec 2018 01:34:49 -0800 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 13 Dec 2018 01:34:49 -0800 Received: from HQMAIL102.nvidia.com (172.18.146.10) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 13 Dec 2018 09:34:49 +0000 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL102.nvidia.com (172.18.146.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 13 Dec 2018 09:34:49 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1395.4 via Frontend Transport; Thu, 13 Dec 2018 09:34:49 +0000 Received: from josephl-linux.nvidia.com (Not Verified[10.19.108.132]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7, 5, 8, 10121) id ; Thu, 13 Dec 2018 01:34:48 -0800 From: Joseph Lo To: Thierry Reding , Peter De Schrijver , Jonathan Hunter CC: , , , Joseph Lo Subject: [PATCH V2 00/21] Tegra210 DFLL support Date: Thu, 13 Dec 2018 17:34:17 +0800 Message-ID: <20181213093438.29621-1-josephl@nvidia.com> X-Mailer: git-send-email 2.19.2 MIME-Version: 1.0 X-NVConfidentiality: public DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1544693686; bh=RxCND4Fg7YVzZJxu87/StswsX1IAY9Y48XVDkN11tzg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: MIME-Version:X-NVConfidentiality:Content-Transfer-Encoding: Content-Type; b=Ii4peS6+9+p1MfniTDmwEhV6nT59LlkuIq32bFmivr4Dh7ojgCUGQyEFggLHxBoby Lif9ekhoPrjT3fo4IEzBNgFmR70femD/bRusBSi8uVnMSE0cUyyZ+vZiGUNE4D3xzN GKQR8arSp41s4fpeAjb3/q0hm1rDTZFP1TD0f2MbHhznFK2GyBj1zJ/0pehWw7VXUl zVV87so4NwAdtgW6kvNMFArG0k0+BLCcYr9fyjRgBr0HemiQRjaDac5GPezzmIR4I5 Vr3jR3BP7JZzl/QVNfXnG0/91UXUa/exwU3RSblX4g1pDOmMF/KYSslVqLj7z42rU/ yfjwROWXyENsA== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This series introduces support for the DFLL as a CPU clock source on Tegra210. As Jetson TX1 uses a PWM controlled regulator IC which is driven directly by the DFLLs PWM output, we also introduce support for PWM regulators next to I2C controlled regulators. The DFLL output frequency is directly controlled by the regulator voltage. The registers for controlling the PWM are part of the DFLL IP block, so there's no separate linux regulator object involved because the regulator IC only supplies the rail powering the CPUs. It doesn't have any other controls. The patch 1~4 are the patches of DT bindings update for DFLL clock and Tegra124 cpufreq, which add PWM and Tegra210 support for DFLL clock and remove deprecate properties for Tegra124 cpufreq bindings. The patch 5~11 are the patches for DFLL clock driver update for PWM-mode DFLL support. The patch 12~14 are the Tegra124 cpufreq driver update to make it work with Tegra210. The patch 15~20 are the devicetree files update for Tegra210 SoC and platforms. Two platforms are updated here for different DFLL mode usage. The Tegra210-p2371-2180 (a.k.a. Jetson Tx1) uses DFLL-PWM and the Tegra210-smaug (a.k.a. Pixel C) uses DFLL-I2C. So two different modes are verified with this series. The patch 21 is the patch for enabling the CPU regulator for Smaug board. * Update in V2: - Add two patches that suggested from comments in V1. See patch 9 and 14. - Update DT binding for DFLL-PWM mode in patch 1. - Update the code for how to get regulator data from DT or regulator API in patch 6. - Update to use lut_uv table for LUT lookup in patch 7. That makes the generic lut table to work with both I2C and PWM mode. - not allow Tegra124 cpufreq driver to be built as a module and remove the removal function in patch 12. Joseph Lo (18): dt-bindings: clock: tegra124-dfll: add Tegra210 support dt-bindings: cpufreq: tegra124: remove vdd-cpu-supply from required properties dt-bindings: cpufreq: tegra124: remove cpu_lp clock from required properties clk: tegra: dfll: CVB calculation alignment with the regulator clk: tegra: dfll: support PWM regulator control clk: tegra: dfll: round down voltages based on alignment clk: tegra: dfll: add protection for find_vdd_map APIs clk: tegra: dfll: add CVB tables for Tegra210 cpufreq: tegra124: do not handle the CPU rail cpufreq: tegra124: extend to support Tegra210 cpufreq: dt-platdev: add Tegra210 to blacklist arm64: dts: tegra210: add DFLL clock arm64: dts: tegra210: add CPU clocks arm64: dts: tegra210-p2597: add pinmux for PWM-based DFLL support arm64: dts: tegra210-p2371-2180: enable DFLL clock arm64: dts: tegra210-smaug: add CPU power rail regulator arm64: dts: tegra210-smaug: enable DFLL clock arm64: defconfig: Enable MAX8973 regulator Peter De Schrijver (3): dt-bindings: clock: tegra124-dfll: Update DFLL binding for PWM regulator clk: tegra: dfll: registration for multiple SoCs clk: tegra: dfll: build clk-dfll.c for Tegra124 and Tegra210 .../bindings/clock/nvidia,tegra124-dfll.txt | 83 ++- .../cpufreq/nvidia,tegra124-cpufreq.txt | 6 +- .../boot/dts/nvidia/tegra210-p2371-2180.dts | 21 + .../arm64/boot/dts/nvidia/tegra210-p2597.dtsi | 14 + arch/arm64/boot/dts/nvidia/tegra210-smaug.dts | 31 + arch/arm64/boot/dts/nvidia/tegra210.dtsi | 25 + arch/arm64/configs/defconfig | 1 + drivers/clk/tegra/Kconfig | 5 + drivers/clk/tegra/Makefile | 2 +- drivers/clk/tegra/clk-dfll.c | 465 ++++++++++++--- drivers/clk/tegra/clk-dfll.h | 6 +- drivers/clk/tegra/clk-tegra124-dfll-fcpu.c | 528 +++++++++++++++++- drivers/clk/tegra/cvb.c | 12 +- drivers/clk/tegra/cvb.h | 7 +- drivers/cpufreq/Kconfig.arm | 4 +- drivers/cpufreq/cpufreq-dt-platdev.c | 1 + drivers/cpufreq/tegra124-cpufreq.c | 44 +- 17 files changed, 1103 insertions(+), 152 deletions(-)