From patchwork Tue May 8 16:26:02 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Osipenko X-Patchwork-Id: 910324 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="dNA0d6LE"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40gQ0h0nchz9s1w for ; Wed, 9 May 2018 02:28:52 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754736AbeEHQ2v (ORCPT ); Tue, 8 May 2018 12:28:51 -0400 Received: from mail-pl0-f65.google.com ([209.85.160.65]:41503 "EHLO mail-pl0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755467AbeEHQ2s (ORCPT ); Tue, 8 May 2018 12:28:48 -0400 Received: by mail-pl0-f65.google.com with SMTP id az12-v6so2530671plb.8; Tue, 08 May 2018 09:28:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=Yf7N8bM5dcNgV4bm7Sa5nXVBCvRoLxDl26zvWPLzQ/M=; b=dNA0d6LEKdhHt/HuyqDlbep8HRFkyo5AwSkZc9CACvaNLYOCmO1mPYKkEjibOCRSaf TSmRG9yLQ4B91U6SYg2974ivIf3aFaP+zTDa3XYmn0arZ2/e5zRVGabP9jctCAVSFWun wjz2Qph9Y/shK2wbcLkFuErhQDLoLcIBaqnijf8keEYvHk1DG5l3D9NaYWzwG9yqQEkv Na/BmPhidzKkO03swL8/Nzz8TiU1160fMsI9TeBT4WTB4rLayrjYWlbKHMesy21ZDi/t SUnSn+6M6vA5y6olsEJxcGACqedSbfkI7BOH6DtqgFZr7ZLAFY/c7YpMPzFgZvSRRVBX 7ZNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Yf7N8bM5dcNgV4bm7Sa5nXVBCvRoLxDl26zvWPLzQ/M=; b=oGBew2sJE82ZkaT40vpujp2zNVUm35TuFCFUxjljhbIROSBeFRTvJEdiNcwHssiNgr 9s7wvQPDZxje+6PLggIe0TNOb1z/kEYPpnslNL7hcAtXx6dW/iTTkNpRLPHqe18GrKHy J9o0/XzxM3lRr6yAMGoeWw2pUQbjNFj5Mfdfw3T6LcuKmHSL2leDT8nWz+MOlOJ1dJj6 sKT/XJ4Q4tTWrmxOrgynwH16P3ukIHTZKM4mEtOuX1CzGiKMc/9LBha4OnbV5JVNjoQu hKQWw7EPlFI+ngJ5ZMO1jEbQO75K6PU1tKEXvy3dKoQwSOHP0zg6G963wchl2zW0D8I3 k/EA== X-Gm-Message-State: ALQs6tCNAuP9Bl88j9gXX3t8dVUakQtj7lZHo2P1A45yCwpyuTVwXm8y ClMM+yrPHQ4xG19F/KOsT14= X-Google-Smtp-Source: AB8JxZo8RRgGNsvPT0BSa7TPFu0CHJ1Cymg7zm5pcq3fX2/JEVyo2r0HZDbAlq+a10olfxLqWTmx9Q== X-Received: by 2002:a17:902:bc48:: with SMTP id t8-v6mr42196148plz.133.1525796927572; Tue, 08 May 2018 09:28:47 -0700 (PDT) Received: from localhost.localdomain ([109.252.91.130]) by smtp.gmail.com with ESMTPSA id o10-v6sm42083664pgc.80.2018.05.08.09.28.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 08 May 2018 09:28:46 -0700 (PDT) From: Dmitry Osipenko To: Thierry Reding , Jonathan Hunter , Peter De Schrijver , Prashant Gaikwad , Stephen Boyd , Michael Turquette , Linus Walleij , Marcel Ziswiler , Marc Dietrich Cc: linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 0/4] Restore ULPI USB on Tegra20 Date: Tue, 8 May 2018 19:26:02 +0300 Message-Id: <20180508162607.3500-1-digetx@gmail.com> X-Mailer: git-send-email 2.17.0 Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org Hello, This series of patches fixes ULPI USB on Tegra20. The original problem was reported by Marcel Ziswiler, he found that "ulpi-link" clock was incorrectly set to CDEV2 instead of PLL_P_OUT4. Marcel made a patch that changed the "ulpi-link" clock to PLL_P_OUT4 and that fixed issue with the USB for the devices that have CDEV2 being enabled by bootloader. The patch got into the kernel and later Marc Dietrich found that USB stopped working on the "paz00" Tegra20 board. After a bit of discussion was revealed that PLL_P_OUT4 is the parent clock of the CDEV2 and clock driver was setting CDEV2's parent incorrectly. The parent clock is actually determined by the pinmuxing config of CDEV2 pingroup. This patchset fixes the parent of CDEV2 clock by making Tegra's pinctrl driver a clock provider, providing CDEV1/2 clock muxes (thanks to Peter De Schrijver for the suggestion), and then setting these clock muxes as parents for the CDEV1/2 clocks. In the end Marcel's CDEV2->PLL_P_OUT4 change is reverted since CDEV2 (aka MCLK2) is the actual clock source for "ulpi-link". Changelog: v3: - Use clk DT ID's instead of comparing clk names and make custom of_src_onecell_get specific to Tegra20 clk provider in the "Add quirk for getting CDEV1/2 clocks on Tegra20" patch as was suggested by Peter De Schrijver for v2. v2: - Added new patch "Add quirk for getting CDEV1/2 clocks", assuring that clk user won't get CDEV1/2 clocks until parent clk muxes are available, i.e. resolves potential issue with CDEV-user driver vs pinctrl driver probe order. - Factored out "pinctrl" patch from the patchset as was requested by Linus Walleij. - Addressed v1 review comments: fixed swapped DEV1/2 clk div bits, made DEV1/2 divs read-only, etc minor changes. Dmitry Osipenko (4): clk: tegra20: Add DEV1/DEV2 OSC dividers clk: tegra20: Correct parents of CDEV1/2 clocks clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20 ARM: dts: tegra20: Revert "Fix ULPI regression on Tegra20" arch/arm/boot/dts/tegra20.dtsi | 2 +- drivers/clk/tegra/clk-tegra114.c | 2 +- drivers/clk/tegra/clk-tegra124.c | 2 +- drivers/clk/tegra/clk-tegra20.c | 52 +++++++++++++++++++++++++++++--- drivers/clk/tegra/clk-tegra210.c | 2 +- drivers/clk/tegra/clk-tegra30.c | 2 +- drivers/clk/tegra/clk.c | 5 +-- drivers/clk/tegra/clk.h | 2 +- 8 files changed, 56 insertions(+), 13 deletions(-)