From patchwork Fri Sep 14 20:02:55 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 970076 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.b="XD3bABOz"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 42Bmfk3BSSz9s3l for ; Sat, 15 Sep 2018 06:03:26 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727760AbeIOBTX (ORCPT ); Fri, 14 Sep 2018 21:19:23 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:5648 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726891AbeIOBTX (ORCPT ); Fri, 14 Sep 2018 21:19:23 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 14 Sep 2018 13:03:28 -0700 Received: from HQMAIL101.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 14 Sep 2018 13:03:24 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 14 Sep 2018 13:03:24 -0700 Received: from tbergstrom-lnx.Nvidia.com (10.124.1.5) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 14 Sep 2018 20:03:24 +0000 Received: from tbergstrom-lnx.nvidia.com (localhost [127.0.0.1]) by tbergstrom-lnx.Nvidia.com (Postfix) with ESMTP id D57D4F80816; Fri, 14 Sep 2018 23:03:18 +0300 (EEST) From: Peter De Schrijver To: , , , , , , CC: , , , Peter De Schrijver Subject: [RFC 00/14] Tegra210 EMC scaling Date: Fri, 14 Sep 2018 23:02:55 +0300 Message-ID: <1536955389-30442-1-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.9.1 X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To HQMAIL101.nvidia.com (172.20.187.10) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1536955408; bh=WfO53tDAnz33DismbmIHB/V/P7rM7x2yKa7cvYkaV9A=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type:X-Originating-IP: X-ClientProxiedBy; b=XD3bABOzpZTmUEOANwnIpETh55eE4RDZUoHAVmb9AUIwBYGtwy6orHfvEMo/IUa8F o770GFnaX96lHmSrWIornLKKcFq0RnBdjB9dFfzAXFF7ektUl4SFFc58INcEXg/qwU m6qCg2tuzEnsSL9RMUoEdACuewulxEJkg9saSVH1DytV45JL/qOeQ+1/87Z0X9rTVG oTCeRN0kyrjGZkovTyC5Pp94i+TIKlgQUFbDVsZw398ar0VR+i/Hp3RJN6fqBk6/Vm 3HQbhyGj4V173kd9kQFlzwrLVOBVj7u1YeBX74/Pgezzm1YmWex5suUqZGT9kg9XKM abexI40X/V/cw== Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This series introduces EMC scaling for Tegra210. It's a preliminary version which hasn't been extensively tested so it may crash your system. The reason I'm posting it anyway to start discussing the DT binding document. The problem here is that this binding is also used by firmware which is already in the field. The firmware needs the data in the DT to perform the initial training and it also writes the results of this training in the DT which are then used by this driver. Without this training higher OPPs cannot be used. Peter De Schrijver (14): memory: tegra: mc: Add Tegra210 MC emem registers clk: tegra: rename emc timing functions clk: tegra: emc: simplify parent matching clk: tegra: emc: prepare for Tegra210 parent table memory: tegra: mc: Introduce helpers memory: tegra: mc: Add support for scaled LA memory: tegra: scaled LA register for Tegra210 clk: tegra: clock changes for emc scaling memory: tegra: Add definitions shared by Tegra210 EMC scaling code memory: tegra: Add Tegra210 EMC scaling sequence memory: tegra: parse DT and costruct timing tables memory: tegra: Tegra210 EMC memory driver memory: tegra: enable Tegra210 EMC scaling driver dt-bindings: tegra: Add Tegra210 EMC binding .../memory-controllers/nvidia,tegra210-emc.txt | 448 ++++ drivers/clk/tegra/clk-emc.c | 88 +- drivers/clk/tegra/clk-tegra210.c | 53 +- drivers/memory/tegra/Kconfig | 10 + drivers/memory/tegra/Makefile | 1 + drivers/memory/tegra/mc.c | 84 +- drivers/memory/tegra/tegra124-emc.c | 8 +- drivers/memory/tegra/tegra210-dt-parse.c | 363 ++++ drivers/memory/tegra/tegra210-emc-cc-r21021.c | 1864 ++++++++++++++++ drivers/memory/tegra/tegra210-emc-reg.h | 1879 ++++++++++++++++ drivers/memory/tegra/tegra210-emc.c | 2268 ++++++++++++++++++++ drivers/memory/tegra/tegra210.c | 99 + include/dt-bindings/clock/tegra210-car.h | 2 + include/soc/tegra/emc.h | 8 +- include/soc/tegra/mc.h | 6 + 15 files changed, 7119 insertions(+), 62 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.txt create mode 100644 drivers/memory/tegra/tegra210-dt-parse.c create mode 100644 drivers/memory/tegra/tegra210-emc-cc-r21021.c create mode 100644 drivers/memory/tegra/tegra210-emc-reg.h create mode 100644 drivers/memory/tegra/tegra210-emc.c