From patchwork Fri Nov 10 11:37:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 836702 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-tegra-owner@vger.kernel.org; receiver=) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3yYJ1j3MG8z9sBW for ; Fri, 10 Nov 2017 22:38:01 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752918AbdKJLh7 (ORCPT ); Fri, 10 Nov 2017 06:37:59 -0500 Received: from hqemgate14.nvidia.com ([216.228.121.143]:12439 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752695AbdKJLh7 (ORCPT ); Fri, 10 Nov 2017 06:37:59 -0500 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com id ; Fri, 10 Nov 2017 03:37:55 -0800 Received: from HQMAIL105.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Fri, 10 Nov 2017 03:38:20 -0800 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Fri, 10 Nov 2017 03:38:20 -0800 Received: from UKMAIL101.nvidia.com (10.26.138.13) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Fri, 10 Nov 2017 11:37:58 +0000 Received: from tbergstrom-lnx.Nvidia.com (10.21.24.170) by UKMAIL101.nvidia.com (10.26.138.13) with Microsoft SMTP Server (TLS) id 15.0.1293.2; Fri, 10 Nov 2017 11:37:54 +0000 Received: from tbergstrom-lnx.Nvidia.com (localhost [127.0.0.1]) by tbergstrom-lnx.Nvidia.com (Postfix) with ESMTP id 02925F80027; Fri, 10 Nov 2017 13:37:54 +0200 (EET) From: Peter De Schrijver To: , CC: Peter De Schrijver Subject: [PATCH 0/4] MBIST WAR for Tegra210 Date: Fri, 10 Nov 2017 13:37:44 +0200 Message-ID: <1510313868-24810-1-git-send-email-pdeschrijver@nvidia.com> X-Mailer: git-send-email 1.9.1 X-NVConfidentiality: public MIME-Version: 1.0 X-Originating-IP: [10.21.24.170] X-ClientProxiedBy: UKMAIL102.nvidia.com (10.26.138.15) To UKMAIL101.nvidia.com (10.26.138.13) Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org This patch series introduces the MBIST WAR needed when power ungating certain domains. More details can be found in 'clk: tegra: MBIST WAR for Tegra210'. I choose to implement the WAR in the Tegra210 clock driver, because most accesses are to CAR registers and for the VENC domain, we need to make sure the CSI clock source is not changed during the WAR execution. Peter De Schrijver (4): clk: tegra: Add la clock for Tegra210 clk: tegra: add fence_delay for clock registers clk: tegra: MBIST WAR for Tegra210 soc/tegra: pmc: apply MBIST WAR for Tegra210 drivers/clk/tegra/clk-tegra210.c | 371 ++++++++++++++++++++++++++++++- drivers/clk/tegra/clk.h | 7 + drivers/soc/tegra/pmc.c | 5 + include/dt-bindings/clock/tegra210-car.h | 2 +- include/linux/clk/tegra.h | 1 + 5 files changed, 383 insertions(+), 3 deletions(-)