diff mbox series

[v6,1/4] arm64: dts: ipq6018: correct TCSR block area

Message ID 889aae1b88f120cb6281919d27164a959fbe69d0.1626948070.git.baruch@tkos.co.il
State Superseded
Headers show
Series [v6,1/4] arm64: dts: ipq6018: correct TCSR block area | expand

Commit Message

Baruch Siach July 22, 2021, 10:01 a.m. UTC 
According to Bjorn Andersson[1], &tcsr_q6 base is 0x01937000 with size
0x21000. Adjust qcom,halt-regs offsets (add 0xe000) to match the new
syscon base.

Also, rename to just &tcsr as Kathiravan T suggested.

[1] https://lore.kernel.org/r/YLgO0Aj1d4w9EcPv@yoga

Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
v6:

  Fix offset adjust (Kathiravan T)

  Rename &tcsr_q6 to &tcsr (Kathiravan T)

v5: New patch in this series
---
 arch/arm64/boot/dts/qcom/ipq6018.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 6ee7b99c21ec..6bb262757cd9 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -270,9 +270,9 @@  tcsr_mutex_regs: syscon@1905000 {
 			reg = <0x0 0x01905000 0x0 0x8000>;
 		};
 
-		tcsr_q6: syscon@1945000 {
+		tcsr: syscon@1937000 {
 			compatible = "syscon";
-			reg = <0x0 0x01945000 0x0 0xe000>;
+			reg = <0x0 0x01937000 0x0 0x21000>;
 		};
 
 		blsp_dma: dma-controller@7884000 {
@@ -615,7 +615,7 @@  q6v5_wcss: remoteproc@cd00000 {
 			clocks = <&gcc GCC_PRNG_AHB_CLK>;
 			clock-names = "prng";
 
-			qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>;
+			qcom,halt-regs = <&tcsr 0x18000 0x1b000 0xe000>;
 
 			qcom,smem-states = <&wcss_smp2p_out 0>,
 					   <&wcss_smp2p_out 1>;