From patchwork Mon Oct 19 17:28:47 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Ayyathurai, Vijayakannan" X-Patchwork-Id: 1384451 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4CFP255HQKz9sSs for ; Tue, 20 Oct 2020 04:31:41 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727772AbgJSRbl (ORCPT ); Mon, 19 Oct 2020 13:31:41 -0400 Received: from mga05.intel.com ([192.55.52.43]:2678 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727022AbgJSRbl (ORCPT ); Mon, 19 Oct 2020 13:31:41 -0400 IronPort-SDR: 3DqzMkBOcALGUyszKAIPyIUGCvHxfRFUjS16FzBUKT4w2w3wVCol7IlLdfx9DLHB36vXhQmLcF X/tnaabD2Tdw== X-IronPort-AV: E=McAfee;i="6000,8403,9779"; a="251766291" X-IronPort-AV: E=Sophos;i="5.77,395,1596524400"; d="scan'208";a="251766291" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2020 10:31:40 -0700 IronPort-SDR: 1HAlOIPZVPjI2OGppiWShtwsDwQhr5yrLjC5nlPnNuj+1cI4Dq0SYqx0djh5qcTaGgwb22VNs4 MjhZX0RqgToQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,395,1596524400"; d="scan'208";a="315737628" Received: from ubuntu18.png.intel.com ([10.88.229.38]) by orsmga003.jf.intel.com with ESMTP; 19 Oct 2020 10:31:38 -0700 From: vijayakannan.ayyathurai@intel.com To: thierry.reding@gmail.com, u.kleine-koenig@pengutronix.de, robh+dt@kernel.org Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, wan.ahmad.zainie.wan.mohamad@intel.com, andriy.shevchenko@linux.intel.com, mgross@linux.intel.com, lakshmi.bai.raja.subramanian@intel.com, vijayakannan.ayyathurai@intel.com Subject: [PATCH v13 2/2] dt-bindings: pwm: keembay: Add bindings for Intel Keem Bay PWM Date: Tue, 20 Oct 2020 01:28:47 +0800 Message-Id: <48f86a9a525701cfc61e3375d1d6f65ce38a9b26.1603127898.git.vijayakannan.ayyathurai@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: In-Reply-To: References: MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Vijayakannan Ayyathurai Add PWM Device Tree bindings documentation for the Intel Keem Bay SoC. Signed-off-by: Vineetha G. Jaya Kumaran Reviewed-by: Rob Herring Acked-by: Uwe Kleine-König Signed-off-by: Vijayakannan Ayyathurai --- .../bindings/pwm/intel,keembay-pwm.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/intel,keembay-pwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/intel,keembay-pwm.yaml b/Documentation/devicetree/bindings/pwm/intel,keembay-pwm.yaml new file mode 100644 index 000000000000..a37433487632 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/intel,keembay-pwm.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Intel Corporation +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/intel,keembay-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay PWM Device Tree Bindings + +maintainers: + - Vineetha G. Jaya Kumaran + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + enum: + - intel,keembay-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 2 + +required: + - compatible + - reg + - clocks + - '#pwm-cells' + +additionalProperties: false + +examples: + - | + #define KEEM_BAY_A53_GPIO + + pwm@203200a0 { + compatible = "intel,keembay-pwm"; + reg = <0x203200a0 0xe8>; + clocks = <&scmi_clk KEEM_BAY_A53_GPIO>; + #pwm-cells = <2>; + };