| Message ID | 20251001-ipq-pwm-v16-7-300f237e0e68@outlook.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add PWM support for IPQ chipsets | expand |
On Wed, Oct 01, 2025 at 06:04:23PM +0400, George Moussalem via B4 Relay wrote: > From: George Moussalem <george.moussalem@outlook.com> > > Describe the PWM block on IPQ5018. > > Although PWM is in the TCSR area, make pwm its own node as simple-mfd > has been removed from the bindings and as such hardware components > should have its own node. > > Signed-off-by: George Moussalem <george.moussalem@outlook.com> > --- > arch/arm64/boot/dts/qcom/ipq5018.dtsi | 10 ++++++++++ > 1 file changed, 10 insertions(+) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> >
diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi index f024b3cba33f6100ac3f4d45598ff2356e026dcf..d4bdf2884aa7f73711cf8a37b7a4c4e7e54c503c 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -453,6 +453,16 @@ tcsr: syscon@1937000 { reg = <0x01937000 0x21000>; }; + pwm: pwm@1941010 { + compatible = "qcom,ipq5018-pwm", "qcom,ipq6018-pwm"; + reg = <0x01941010 0x20>; + clocks = <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates = <100000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + sdhc_1: mmc@7804000 { compatible = "qcom,ipq5018-sdhci", "qcom,sdhci-msm-v5"; reg = <0x7804000 0x1000>;