| Message ID | 20240212210652.368680-2-fabrizio.castro.jz@renesas.com |
|---|---|
| State | Changes Requested |
| Headers | show |
| Series | Add RZ/V2{M, MA} PWM driver support | expand |
On Mon, Feb 12, 2024 at 09:06:49PM +0000, Fabrizio Castro wrote: > From: Biju Das <biju.das.jz@bp.renesas.com> > > Add device tree bindings for the RZ/V2{M, MA} PWM Timer (PWM). > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> If you send a patch, it needs your S-o-b. (Though you could probably trick me into applying v6 :-) Best regards Uwe
Hi Uwe, thanks for your feedback. I'll add my S-o-b in v8. Cheers, Fab > -----Original Message----- > From: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> > Sent: Thursday, February 29, 2024 4:22 PM > To: Fabrizio Castro <fabrizio.castro.jz@renesas.com> > Cc: Rob Herring <robh@kernel.org>; Krzysztof Kozlowski > <krzysztof.kozlowski+dt@linaro.org>; Conor Dooley <conor+dt@kernel.org>; > Geert Uytterhoeven <geert+renesas@glider.be>; Biju Das > <biju.das.jz@bp.renesas.com>; Magnus Damm <magnus.damm@gmail.com>; linux- > pwm@vger.kernel.org; devicetree@vger.kernel.org; linux- > kernel@vger.kernel.org; linux-renesas-soc@vger.kernel.org; Krzysztof > Kozlowski <krzysztof.kozlowski@linaro.org> > Subject: Re: [PATCH v7 1/4] dt-bindings: pwm: Add RZ/V2M PWM binding > > On Mon, Feb 12, 2024 at 09:06:49PM +0000, Fabrizio Castro wrote: > > From: Biju Das <biju.das.jz@bp.renesas.com> > > > > Add device tree bindings for the RZ/V2{M, MA} PWM Timer (PWM). > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> > > If you send a patch, it needs your S-o-b. (Though you could probably > trick me into applying v6 :-) > > Best regards > Uwe > > -- > Pengutronix e.K. | Uwe Kleine-König | > Industrial Linux Solutions | https://www.pengutronix.de/ |
diff --git a/Documentation/devicetree/bindings/pwm/renesas,rzv2m-pwm.yaml b/Documentation/devicetree/bindings/pwm/renesas,rzv2m-pwm.yaml new file mode 100644 index 000000000000..ddeed7550923 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/renesas,rzv2m-pwm.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/renesas,rzv2m-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2{M, MA} PWM Timer (PWM) + +maintainers: + - Biju Das <biju.das.jz@bp.renesas.com> + +description: | + The RZ/V2{M, MA} PWM Timer (PWM) composed of 16 channels. It supports the + following functions + * The PWM has 24-bit counters which operate at PWM_CLK (48 MHz). + * The frequency division ratio for internal counter operation is selectable + as PWM_CLK divided by 1, 16, 256, or 2048. + * The period as well as the duty cycle is adjustable. + * The low-level and high-level order of the PWM signals can be inverted. + * The duty cycle of the PWM signal is selectable in the range from 0 to 100%. + * The minimum resolution is 20.83 ns. + * Three interrupt sources: Rising and falling edges of the PWM signal and + clearing of the counter + * Counter operation and the bus interface are asynchronous and both can + operate independently of the magnitude relationship of the respective + clock periods. + +properties: + compatible: + items: + - enum: + - renesas,r9a09g011-pwm # RZ/V2M + - renesas,r9a09g055-pwm # RZ/V2MA + - const: renesas,rzv2m-pwm + + reg: + maxItems: 1 + + '#pwm-cells': + const: 2 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: APB clock + - description: PWM clock + + clock-names: + items: + - const: apb + - const: pwm + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + - resets + +allOf: + - $ref: pwm.yaml# + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r9a09g011-cpg.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pwm8: pwm@a4010400 { + compatible = "renesas,r9a09g011-pwm", "renesas,rzv2m-pwm"; + reg = <0xa4010400 0x80>; + interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A09G011_CPERI_GRPF_PCLK>, + <&cpg CPG_MOD R9A09G011_PWM8_CLK>; + clock-names = "apb", "pwm"; + power-domains = <&cpg>; + resets = <&cpg R9A09G011_PWM_GPF_PRESETN>; + #pwm-cells = <2>; + };