| Message ID | 20191108084517.21617-5-peron.clem@gmail.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | Add support for H6 PWM | expand |
On Fri, Nov 08, 2019 at 09:45:14AM +0100, Clément Péron wrote: > From: Jernej Skrabec <jernej.skrabec@siol.net> > > PWM core has an option to bypass whole logic and output unchanged source > clock as PWM output. This is achieved by enabling bypass bit. > > Note that when bypass is enabled, no other setting has any meaning, not > even enable bit. > > This mode of operation is needed to achieve high enough frequency to > serve as clock source for AC200 chip which is integrated into same > package as H6 SoC. > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > Signed-off-by: Clément Péron <peron.clem@gmail.com> > --- > drivers/pwm/pwm-sun4i.c | 44 +++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 44 insertions(+) > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > index a10022d6c0fd..9cc928ab47bc 100644 > --- a/drivers/pwm/pwm-sun4i.c > +++ b/drivers/pwm/pwm-sun4i.c > @@ -3,6 +3,10 @@ > * Driver for Allwinner sun4i Pulse Width Modulation Controller > * > * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com> > + * > + * Limitations: > + * - When outputing the source clock directly, the PWM logic will be bypassed > + * and the currently running period is not guaranteed to be completed > */ > > #include <linux/bitops.h> > @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = { > > struct sun4i_pwm_data { > bool has_prescaler_bypass; > + bool has_direct_mod_clk_output; > unsigned int npwm; > }; > > @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, > > val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); > > + /* > + * PWM chapter in H6 manual has a diagram which explains that if bypass > + * bit is set, no other setting has any meaning. Even more, experiment > + * proved that also enable bit is ignored in this case. > + */ > + if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && > + sun4i_pwm->data->has_direct_mod_clk_output) { > + state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); > + state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2); I first thought you're losing precision here by reusing state->period here, but with a divisor of 2 everything is fine. > + state->polarity = PWM_POLARITY_NORMAL; > + state->enabled = true; > + return; > + } > + > if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && > sun4i_pwm->data->has_prescaler_bypass) > prescaler = 1; > @@ -204,6 +223,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); > struct pwm_state cstate; > u32 ctrl; > + bool bypass = false; > int ret; > unsigned int delay_us; > unsigned long now; > @@ -218,9 +238,24 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > } > } > > + /* > + * Although it would make much more sense to check for bypass in > + * sun4i_pwm_calculate(), value of bypass bit also depends on "enabled". I don't understand this reasoning. sun4i_pwm_calculate knows about .enabled and also sun4i_pwm->data->has_direct_mod_clk_output. Maybe just add a bool *bypass as parameter and move the logic there? > + */ > + if (state->enabled) { > + u32 clk_rate = clk_get_rate(sun4i_pwm->clk); > + bypass = (state->period * clk_rate >= NSEC_PER_SEC) && > + (state->period * clk_rate < 2 * NSEC_PER_SEC) && > + (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC); > + } > + This looks right now. Best regards Uwe
Hi Uwe, On Wed, 13 Nov 2019 at 09:58, Uwe Kleine-König <u.kleine-koenig@pengutronix.de> wrote: > > On Fri, Nov 08, 2019 at 09:45:14AM +0100, Clément Péron wrote: > > From: Jernej Skrabec <jernej.skrabec@siol.net> > > > > PWM core has an option to bypass whole logic and output unchanged source > > clock as PWM output. This is achieved by enabling bypass bit. > > > > Note that when bypass is enabled, no other setting has any meaning, not > > even enable bit. > > > > This mode of operation is needed to achieve high enough frequency to > > serve as clock source for AC200 chip which is integrated into same > > package as H6 SoC. > > > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > > Signed-off-by: Clément Péron <peron.clem@gmail.com> > > --- > > drivers/pwm/pwm-sun4i.c | 44 +++++++++++++++++++++++++++++++++++++++++ > > 1 file changed, 44 insertions(+) > > > > diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c > > index a10022d6c0fd..9cc928ab47bc 100644 > > --- a/drivers/pwm/pwm-sun4i.c > > +++ b/drivers/pwm/pwm-sun4i.c > > @@ -3,6 +3,10 @@ > > * Driver for Allwinner sun4i Pulse Width Modulation Controller > > * > > * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com> > > + * > > + * Limitations: > > + * - When outputing the source clock directly, the PWM logic will be bypassed > > + * and the currently running period is not guaranteed to be completed > > */ > > > > #include <linux/bitops.h> > > @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = { > > > > struct sun4i_pwm_data { > > bool has_prescaler_bypass; > > + bool has_direct_mod_clk_output; > > unsigned int npwm; > > }; > > > > @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, > > > > val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); > > > > + /* > > + * PWM chapter in H6 manual has a diagram which explains that if bypass > > + * bit is set, no other setting has any meaning. Even more, experiment > > + * proved that also enable bit is ignored in this case. > > + */ > > + if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && > > + sun4i_pwm->data->has_direct_mod_clk_output) { > > + state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); > > + state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2); > > I first thought you're losing precision here by reusing state->period > here, but with a divisor of 2 everything is fine. > > > + state->polarity = PWM_POLARITY_NORMAL; > > + state->enabled = true; > > + return; > > + } > > + > > if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && > > sun4i_pwm->data->has_prescaler_bypass) > > prescaler = 1; > > @@ -204,6 +223,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > > struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); > > struct pwm_state cstate; > > u32 ctrl; > > + bool bypass = false; > > int ret; > > unsigned int delay_us; > > unsigned long now; > > @@ -218,9 +238,24 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > > } > > } > > > > + /* > > + * Although it would make much more sense to check for bypass in > > + * sun4i_pwm_calculate(), value of bypass bit also depends on "enabled". > > I don't understand this reasoning. sun4i_pwm_calculate knows about > .enabled and also sun4i_pwm->data->has_direct_mod_clk_output. Maybe just > add a bool *bypass as parameter and move the logic there? I asked myself the same question, however the sun4i_pwm_calculate is only called when period or duty_cycle is updated not when state is toggled between disabled / enabled. Should we also call it when the state is switched to enabled ? Regards, Clément > > > + */ > > + if (state->enabled) { > > + u32 clk_rate = clk_get_rate(sun4i_pwm->clk); > > + bypass = (state->period * clk_rate >= NSEC_PER_SEC) && > > + (state->period * clk_rate < 2 * NSEC_PER_SEC) && > > + (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC); > > + } > > + > > This looks right now. > > Best regards > Uwe > > -- > Pengutronix e.K. | Uwe Kleine-König | > Industrial Linux Solutions | https://www.pengutronix.de/ |
Hello Clément, On Thu, Nov 14, 2019 at 11:47:00PM +0100, Clément Péron wrote: > On Wed, 13 Nov 2019 at 09:58, Uwe Kleine-König > <u.kleine-koenig@pengutronix.de> wrote: > > On Fri, Nov 08, 2019 at 09:45:14AM +0100, Clément Péron wrote: > > > From: Jernej Skrabec <jernej.skrabec@siol.net> > > > + /* > > > + * Although it would make much more sense to check for bypass in > > > + * sun4i_pwm_calculate(), value of bypass bit also depends on "enabled". > > > > I don't understand this reasoning. sun4i_pwm_calculate knows about > > .enabled and also sun4i_pwm->data->has_direct_mod_clk_output. Maybe just > > add a bool *bypass as parameter and move the logic there? > > I asked myself the same question, however the sun4i_pwm_calculate is > only called when period or duty_cycle is updated not when state is > toggled between disabled / enabled. > > Should we also call it when the state is switched to enabled ? Given that the check if ((cstate.period != state->period) || (cstate.duty_cycle != state->duty_cycle)) { is not perfect anyhow (because if I toggle between pwm_apply_state(pwm, { .period = 50000001, .duty_cycle = 25000000, .enabled = true }); and pwm_apply_state(pwm, { .period = 50000000, .duty_cycle = 25000000, .enabled = true }); the code recalculates every parameter while it (probably) doesn't make a difference.) And also given that cstate is filled by pwm_get_state which might change its semantic slightly in the future I would say calculating the needed parameter always is also cleaner. (But I'm aware this isn't objective enough to overrule different opinions.) While I'm a fan of avoid unneeded calculations, I think having a simple driver is more important. (And apart from that I don't like lowlevel drivers calling the pwm API that is designed for consumers.) Best regards Uwe
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index a10022d6c0fd..9cc928ab47bc 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -3,6 +3,10 @@ * Driver for Allwinner sun4i Pulse Width Modulation Controller * * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com> + * + * Limitations: + * - When outputing the source clock directly, the PWM logic will be bypassed + * and the currently running period is not guaranteed to be completed */ #include <linux/bitops.h> @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = { struct sun4i_pwm_data { bool has_prescaler_bypass; + bool has_direct_mod_clk_output; unsigned int npwm; }; @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); + /* + * PWM chapter in H6 manual has a diagram which explains that if bypass + * bit is set, no other setting has any meaning. Even more, experiment + * proved that also enable bit is ignored in this case. + */ + if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && + sun4i_pwm->data->has_direct_mod_clk_output) { + state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate); + state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2); + state->polarity = PWM_POLARITY_NORMAL; + state->enabled = true; + return; + } + if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && sun4i_pwm->data->has_prescaler_bypass) prescaler = 1; @@ -204,6 +223,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); struct pwm_state cstate; u32 ctrl; + bool bypass = false; int ret; unsigned int delay_us; unsigned long now; @@ -218,9 +238,24 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, } } + /* + * Although it would make much more sense to check for bypass in + * sun4i_pwm_calculate(), value of bypass bit also depends on "enabled". + */ + if (state->enabled) { + u32 clk_rate = clk_get_rate(sun4i_pwm->clk); + bypass = (state->period * clk_rate >= NSEC_PER_SEC) && + (state->period * clk_rate < 2 * NSEC_PER_SEC) && + (state->duty_cycle * clk_rate * 2 >= NSEC_PER_SEC); + } + spin_lock(&sun4i_pwm->ctrl_lock); ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); + /* We can skip calculation and apply parameters */ + if (bypass && sun4i_pwm->data->has_direct_mod_clk_output) + goto bypass_mode; + if ((cstate.period != state->period) || (cstate.duty_cycle != state->duty_cycle)) { u32 period, duty, val; @@ -258,6 +293,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm); ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm); + if (state->enabled) { ctrl |= BIT_CH(PWM_EN, pwm->hwpwm); } else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) { @@ -265,6 +301,14 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); } +bypass_mode: + if (sun4i_pwm->data->has_direct_mod_clk_output) { + if (bypass) + ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); + else + ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); + } + sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); spin_unlock(&sun4i_pwm->ctrl_lock);