From patchwork Wed Apr 12 16:33:20 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thierry Reding X-Patchwork-Id: 750067 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3w38cb17ylz9s0g for ; Thu, 13 Apr 2017 02:33:35 +1000 (AEST) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="LrzLSvFu"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754966AbdDLQdd (ORCPT ); Wed, 12 Apr 2017 12:33:33 -0400 Received: from mail-wm0-f66.google.com ([74.125.82.66]:33037 "EHLO mail-wm0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752731AbdDLQd2 (ORCPT ); Wed, 12 Apr 2017 12:33:28 -0400 Received: by mail-wm0-f66.google.com with SMTP id o81so7535400wmb.0; Wed, 12 Apr 2017 09:33:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=cmt7h4PXT2a0d3O9f6Fv0vS6wHpnzQksTi6AYFI3l1k=; b=LrzLSvFuOnebPRNiLcFdSX/AcdqLfcWvx4F6E4LTSysExIgS8fYUp6p4aJZhcxJIjI qB5G8/8Rm+6dW3IPou9f+noDk/zmukTslIycXW+Q+IvPGOVZ5E8cRFBZcbo6+N239L4S GCRF3lQ6OxoPwEdhubt9u7eC/okXRyROGhd7mYYDtf8fgr2f8kI72ucY19ZKE0IqN23r CA1rkMaQDbOLwrGPbrJgxVmZ5zQHVLaFP9Gb0pqJWYNkXlsITtBhPpA/Rola4mKCAHhs 0UQuVCdBNZIvAYzPHOpYSon6/3j983mvfWSgASK0GjC/AS+vsG0bpM9ALk1e0vd18LRi p8MQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=cmt7h4PXT2a0d3O9f6Fv0vS6wHpnzQksTi6AYFI3l1k=; b=r8nuCe5nr9nmLVA/6fF5uNj7CekLkVV5tWOcPW0515BewAdui9TvIReKbZ/LjMKDjc eqZsiewRbQCZfcTonQG7RCXR6QJksUDcbP7soB+FvZKjuySzPCruHwDrDYx35/97lF79 UNNcdWVRx2K4ghXztOsCPsck2yKjPVelAKgLr/Vjyk1jaw1Tt6zpzE5CSp1ftMhz733h 4ssdBaEkmzOAe3Hc2Du8XXb3jBLPfSaFSA1SOU7lHcGTAXbAWVhkfTNSAQVNMADeC36E Rr0wibcEfOxcWSX5Dd7mgOmJ2PbXqcKe708LA6CUcLAOLw1/nU6cHXtcc98dtU/kmkVZ Hycw== X-Gm-Message-State: AN3rC/7Yc9vsQxfcOsLO/s7vdv2MD3b2GNNW6xXT3cfGSPBTLCfVpUusjXy6toLl0BRfAQ== X-Received: by 10.28.74.209 with SMTP id n78mr3708373wmi.64.1492014801847; Wed, 12 Apr 2017 09:33:21 -0700 (PDT) Received: from localhost (port-57131.pppoe.wtnet.de. [46.59.223.227]) by smtp.gmail.com with ESMTPSA id 140sm7214599wmg.18.2017.04.12.09.33.21 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 12 Apr 2017 09:33:21 -0700 (PDT) From: Thierry Reding To: Thierry Reding Cc: Jon Hunter , Laxman Dewangan , linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org Subject: [PATCH] pwm: tegra: Avoid potential overflow for short periods Date: Wed, 12 Apr 2017 18:33:20 +0200 Message-Id: <20170412163320.11760-1-thierry.reding@gmail.com> X-Mailer: git-send-email 2.12.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org For very short periods, the result of the division might overflow the unsigned long hz variable (on 32-bit architectures). Avoid that by making it an unsigned long long. While at it, also remove an unneeded local variable whose only purpose is to store a temporary computation. Signed-off-by: Thierry Reding Acked-by: Laxman Dewangan --- drivers/pwm/pwm-tegra.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c index 9c7f180b9f3a..c040f87ee144 100644 --- a/drivers/pwm/pwm-tegra.c +++ b/drivers/pwm/pwm-tegra.c @@ -75,9 +75,8 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, int duty_ns, int period_ns) { struct tegra_pwm_chip *pc = to_tegra_pwm_chip(chip); - unsigned long long c = duty_ns; - unsigned long rate, hz; - unsigned long long ns100 = NSEC_PER_SEC; + unsigned long long c = duty_ns, hz; + unsigned long rate; u32 val = 0; int err; @@ -98,9 +97,8 @@ static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, rate = clk_get_rate(pc->clk) >> PWM_DUTY_WIDTH; /* Consider precision in PWM_SCALE_WIDTH rate calculation */ - ns100 *= 100; - hz = DIV_ROUND_CLOSEST_ULL(ns100, period_ns); - rate = DIV_ROUND_CLOSEST(rate * 100, hz); + hz = DIV_ROUND_CLOSEST_ULL(100ULL * NSEC_PER_SEC, period_ns); + rate = DIV_ROUND_CLOSEST_ULL(100ULL * rate, hz); /* * Since the actual PWM divider is the register's frequency divider