From patchwork Sat Aug 22 14:30:46 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "G Jaya Kumaran, Vineetha" X-Patchwork-Id: 1349672 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=intel.com Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 4BYgnh5m5zz9sPf for ; Sun, 23 Aug 2020 00:32:08 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728134AbgHVOcI (ORCPT ); Sat, 22 Aug 2020 10:32:08 -0400 Received: from mga03.intel.com ([134.134.136.65]:6683 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727899AbgHVOcG (ORCPT ); Sat, 22 Aug 2020 10:32:06 -0400 IronPort-SDR: g6iUjQZwQZB2esvasnQRap43NCeMGl9Pnu1Kp3/UPPNTikCHIb5LOJFgHkr0bp2YKlpkUh+lD7 HTwkv8IHLPAw== X-IronPort-AV: E=McAfee;i="6000,8403,9720"; a="155690643" X-IronPort-AV: E=Sophos;i="5.76,341,1592895600"; d="scan'208";a="155690643" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Aug 2020 07:32:06 -0700 IronPort-SDR: bjm43Wm68XMJqAAUyIM94sUzNCzJDjyCaynpt6z7JJR+Bym7QmeXM+QbfQNsqgJUxCGcda2B4s BlReRPpSt3fA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,341,1592895600"; d="scan'208";a="335569346" Received: from vgjayaku-ilbpg7.png.intel.com ([10.88.227.96]) by FMSMGA003.fm.intel.com with ESMTP; 22 Aug 2020 07:32:04 -0700 From: vineetha.g.jaya.kumaran@intel.com To: thierry.reding@gmail.com, u.kleine-koenig@pengutronix.de, robh+dt@kernel.org Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, wan.ahmad.zainie.wan.mohamad@intel.com, andriy.shevchenko@intel.com, lakshmi.bai.raja.subramanian@intel.com Subject: [PATCH v4 2/2] dt-bindings: pwm: keembay: Add bindings for Intel Keem Bay PWM Date: Sat, 22 Aug 2020 22:30:46 +0800 Message-Id: <1598106646-16595-3-git-send-email-vineetha.g.jaya.kumaran@intel.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1598106646-16595-1-git-send-email-vineetha.g.jaya.kumaran@intel.com> References: <1598106646-16595-1-git-send-email-vineetha.g.jaya.kumaran@intel.com> Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: "Vineetha G. Jaya Kumaran" Add PWM Device Tree bindings documentation for the Intel Keem Bay SoC. Reviewed-by: Rob Herring Signed-off-by: Vineetha G. Jaya Kumaran --- .../devicetree/bindings/pwm/intel,keembay-pwm.yaml | 47 ++++++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/intel,keembay-pwm.yaml diff --git a/Documentation/devicetree/bindings/pwm/intel,keembay-pwm.yaml b/Documentation/devicetree/bindings/pwm/intel,keembay-pwm.yaml new file mode 100644 index 00000000..a374334 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/intel,keembay-pwm.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 Intel Corporation +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/intel,keembay-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay PWM Device Tree Bindings + +maintainers: + - Vineetha G. Jaya Kumaran + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + enum: + - intel,keembay-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 2 + +required: + - compatible + - reg + - clocks + - '#pwm-cells' + +additionalProperties: false + +examples: + - | + #define KEEM_BAY_A53_GPIO + + pwm@203200a0 { + compatible = "intel,keembay-pwm"; + reg = <0x203200a0 0xe8>; + clocks = <&scmi_clk KEEM_BAY_A53_GPIO>; + #pwm-cells = <2>; + };