From patchwork Mon Jun 1 06:19:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sandipan Patra X-Patchwork-Id: 1301595 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org (client-ip=23.128.96.18; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=nvidia.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=nvidia.com header.i=@nvidia.com header.a=rsa-sha256 header.s=n1 header.b=o9bomi6d; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by ozlabs.org (Postfix) with ESMTP id 49b4l76t4Vz9sT9 for ; Mon, 1 Jun 2020 16:19:31 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726142AbgFAGT1 (ORCPT ); Mon, 1 Jun 2020 02:19:27 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:3280 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725778AbgFAGT0 (ORCPT ); Mon, 1 Jun 2020 02:19:26 -0400 Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Sun, 31 May 2020 23:19:14 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate102.nvidia.com (PGP Universal service); Sun, 31 May 2020 23:19:26 -0700 X-PGP-Universal: processed; by hqpgpgate102.nvidia.com on Sun, 31 May 2020 23:19:26 -0700 Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 1 Jun 2020 06:19:25 +0000 Received: from rnnvemgw01.nvidia.com (10.128.109.123) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Mon, 1 Jun 2020 06:19:25 +0000 Received: from sandipan-pc.nvidia.com (Not Verified[10.24.42.163]) by rnnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Sun, 31 May 2020 23:19:24 -0700 From: Sandipan Patra To: , , , , , , CC: , , , , , , , , Sandipan Patra Subject: [PATCH V2 1/2] hwmon: pwm-fan: Add profile support and add remove module support Date: Mon, 1 Jun 2020 11:49:13 +0530 Message-ID: <1590992354-12623-1-git-send-email-spatra@nvidia.com> X-Mailer: git-send-email 2.7.4 X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1590992354; bh=sYoUNsGo245JmVJN7wCzaJp9QmYtBmfTy0LfKikZk5I=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: X-NVConfidentiality:MIME-Version:Content-Type; b=o9bomi6d7dTTihpcjgpx+2XNZBXEpqVSaysojW9uV9MLLzJX7b9TSG+hEQnhbvqlI i6a+9WOj73uOLoazIAI7JW/ZgrZesvaCR6nfjzIP3/UpC3CpITGtFJDhc7OhN0Kg7U kwViLSTOoI1GUGGOqtASoe27B6w7CRZPCV9sTTaIryQB9zKAd8bLqnKR8RJIQxrdO3 y4JOcko427vfeGAWXTK0VZeHHCN17WZ9vdd67iNcWuNMTyCjplsPwyY+ZVEklpBVjU WYdJY0Liv/wNSTSG+UyBM/BQT/155HFJRFRtyJpbbxAHIEDdqowcaPbZujDpB9J4Jb /EhUC0rRyIgAw== Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Add support for profiles mode settings. This allows different fan settings for trip point temp/hyst/pwm. Tegra194 has multiple fan-profiles support. Signed-off-by: Sandipan Patra --- PATCH V2: Cleaned pwm_fan_remove support as it is not required. drivers/hwmon/pwm-fan.c | 92 ++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 80 insertions(+), 12 deletions(-) diff --git a/drivers/hwmon/pwm-fan.c b/drivers/hwmon/pwm-fan.c index 30b7b3e..1d2a416 100644 --- a/drivers/hwmon/pwm-fan.c +++ b/drivers/hwmon/pwm-fan.c @@ -3,8 +3,10 @@ * pwm-fan.c - Hwmon driver for fans connected to PWM lines. * * Copyright (c) 2014 Samsung Electronics Co., Ltd. + * Copyright (c) 2020, NVIDIA Corporation. * * Author: Kamil Debski + * Author: Sandipan Patra */ #include @@ -21,6 +23,8 @@ #include #define MAX_PWM 255 +/* Based on OF max device tree node name length */ +#define MAX_PROFILE_NAME_LENGTH 31 struct pwm_fan_ctx { struct mutex lock; @@ -38,6 +42,12 @@ struct pwm_fan_ctx { unsigned int pwm_fan_state; unsigned int pwm_fan_max_state; unsigned int *pwm_fan_cooling_levels; + + unsigned int pwm_fan_profiles; + const char **fan_profile_names; + unsigned int **fan_profile_cooling_levels; + unsigned int fan_current_profile; + struct thermal_cooling_device *cdev; }; @@ -227,28 +237,86 @@ static int pwm_fan_of_get_cooling_data(struct device *dev, struct pwm_fan_ctx *ctx) { struct device_node *np = dev->of_node; + struct device_node *base_profile = NULL; + struct device_node *profile_np = NULL; + const char *default_profile = NULL; int num, i, ret; - if (!of_find_property(np, "cooling-levels", NULL)) - return 0; + num = of_property_count_u32_elems(np, "cooling-levels"); + if (num <= 0) { + base_profile = of_get_child_by_name(np, "profiles"); + if (!base_profile) { + dev_err(dev, "Wrong Data\n"); + return -EINVAL; + } + } + + if (base_profile) { + ctx->pwm_fan_profiles = + of_get_available_child_count(base_profile); - ret = of_property_count_u32_elems(np, "cooling-levels"); - if (ret <= 0) { - dev_err(dev, "Wrong data!\n"); - return ret ? : -EINVAL; + if (ctx->pwm_fan_profiles <= 0) { + dev_err(dev, "Profiles used but not defined\n"); + return -EINVAL; + } + + ctx->fan_profile_names = devm_kzalloc(dev, + sizeof(const char *) * ctx->pwm_fan_profiles, + GFP_KERNEL); + ctx->fan_profile_cooling_levels = devm_kzalloc(dev, + sizeof(int *) * ctx->pwm_fan_profiles, + GFP_KERNEL); + + if (!ctx->fan_profile_names + || !ctx->fan_profile_cooling_levels) + return -ENOMEM; + + ctx->fan_current_profile = 0; + i = 0; + for_each_available_child_of_node(base_profile, profile_np) { + num = of_property_count_u32_elems(profile_np, + "cooling-levels"); + if (num <= 0) { + dev_err(dev, "No data in cooling-levels inside profile node!\n"); + return -EINVAL; + } + + of_property_read_string(profile_np, "name", + &ctx->fan_profile_names[i]); + if (default_profile && + !strncmp(default_profile, + ctx->fan_profile_names[i], + MAX_PROFILE_NAME_LENGTH)) + ctx->fan_current_profile = i; + + ctx->fan_profile_cooling_levels[i] = + devm_kzalloc(dev, sizeof(int) * num, + GFP_KERNEL); + if (!ctx->fan_profile_cooling_levels[i]) + return -ENOMEM; + + of_property_read_u32_array(profile_np, "cooling-levels", + ctx->fan_profile_cooling_levels[i], num); + i++; + } } - num = ret; ctx->pwm_fan_cooling_levels = devm_kcalloc(dev, num, sizeof(u32), GFP_KERNEL); if (!ctx->pwm_fan_cooling_levels) return -ENOMEM; - ret = of_property_read_u32_array(np, "cooling-levels", - ctx->pwm_fan_cooling_levels, num); - if (ret) { - dev_err(dev, "Property 'cooling-levels' cannot be read!\n"); - return ret; + if (base_profile) { + memcpy(ctx->pwm_fan_cooling_levels, + ctx->fan_profile_cooling_levels[ctx->fan_current_profile], + num); + } else { + ret = of_property_read_u32_array(np, "cooling-levels", + ctx->pwm_fan_cooling_levels, num); + if (ret) { + dev_err(dev, "Property 'cooling-levels' cannot be read!\n"); + return -EINVAL; + } } for (i = 0; i < num; i++) {