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Thu, 25 Apr 2019 12:28:26 +0000 Received: from MWHPR11MB1549.namprd11.prod.outlook.com ([fe80::f01a:9325:7a65:cdb4]) by MWHPR11MB1549.namprd11.prod.outlook.com ([fe80::f01a:9325:7a65:cdb4%4]) with mapi id 15.20.1813.017; Thu, 25 Apr 2019 12:28:26 +0000 From: To: , , , , , , CC: , , , , Subject: [PATCH v3 1/6] drm: atmel-hlcdc: add config option for clock selection Thread-Topic: [PATCH v3 1/6] drm: atmel-hlcdc: add config option for clock selection Thread-Index: AQHU+2JhBuWnQ7wyq02aSqvKdcdQ3Q== Date: Thu, 25 Apr 2019 12:28:26 +0000 Message-ID: <1556195285-10687-2-git-send-email-claudiu.beznea@microchip.com> References: <1556195285-10687-1-git-send-email-claudiu.beznea@microchip.com> In-Reply-To: <1556195285-10687-1-git-send-email-claudiu.beznea@microchip.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: VI1PR07CA0254.eurprd07.prod.outlook.com (2603:10a6:803:b4::21) To MWHPR11MB1549.namprd11.prod.outlook.com (2603:10b6:301:c::17) authentication-results: spf=none (sender IP is ) smtp.mailfrom=Claudiu.Beznea@microchip.com; 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DIR:OUT; SFP:1101; SCL:1; SRVR:MWHPR11MB1470; H:MWHPR11MB1549.namprd11.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: microchip.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: F3FjGzo7i4S3ISNsM+0Z5nRjxOYx47eulEvwtKyRtjY4pHuTFTQt1buGus/KdC3qEPWpVFtfBUlIxQitRSZP9EjLdbxNuxc1Z9lPg+UyvCZyMFN13/sV+KwCcPNOvkLD+0MsJKMpXovxg3+aTWdi0xG+p7uhWb6mGP65k2SxhYnJpVSifqUxqcETD3/MAKZaLfsPc3J0vcap07ikH12WDZhnTZ/qMDr841VB3nSThkzJ1sga0jOZHxl2txm80oyUSDNIy0ZHzjiTLqgRqAW9z2s8pN8cLf37xHzbdPaHLxjpZNcufI3Yld0d6CutqDHchh+KZcMLg0OtwSeC7PbOHXidFdq5fnhZuN2CHNIS4MKN4MOkNGM7V2q6kPdu8JqMF8eTZ9mjjdr8UtUtQTGGH35K9rhLuvzcG7uiuPh1uoY= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 0c5612fc-4df4-45b6-4277-08d6c97983cd X-MS-Exchange-CrossTenant-originalarrivaltime: 25 Apr 2019 12:28:26.2870 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR11MB1470 X-OriginatorOrg: microchip.com Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Claudiu Beznea SAM9x60 LCD Controller has no option to select clock source as previous controllers have. To be able to use the same driver even for this LCD controller add a config option to know if controller supports this. Signed-off-by: Claudiu Beznea Reviewed-by: Sam Ravnborg --- drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 12 +++++++----- drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h | 2 ++ 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c index 8070a558d7b1..957e6d2fb00f 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c @@ -78,7 +78,8 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) unsigned long mode_rate; struct videomode vm; unsigned long prate; - unsigned int cfg; + unsigned int mask = ATMEL_HLCDC_CLKDIV_MASK | ATMEL_HLCDC_CLKPOL; + unsigned int cfg = 0; int div; vm.vfront_porch = adj->crtc_vsync_start - adj->crtc_vdisplay; @@ -101,7 +102,10 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) (adj->crtc_hdisplay - 1) | ((adj->crtc_vdisplay - 1) << 16)); - cfg = ATMEL_HLCDC_CLKSEL; + if (!crtc->dc->desc->fixed_clksrc) { + cfg |= ATMEL_HLCDC_CLKSEL; + mask |= ATMEL_HLCDC_CLKSEL; + } prate = 2 * clk_get_rate(crtc->dc->hlcdc->sys_clk); mode_rate = adj->crtc_clock * 1000; @@ -132,9 +136,7 @@ static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) cfg |= ATMEL_HLCDC_CLKDIV(div); - regmap_update_bits(regmap, ATMEL_HLCDC_CFG(0), - ATMEL_HLCDC_CLKSEL | ATMEL_HLCDC_CLKDIV_MASK | - ATMEL_HLCDC_CLKPOL, cfg); + regmap_update_bits(regmap, ATMEL_HLCDC_CFG(0), mask, cfg); cfg = 0; diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h index 70bd540d644e..0155efb9c443 100644 --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.h @@ -328,6 +328,7 @@ atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer *layer) * @max_hpw: maximum horizontal back/front porch width * @conflicting_output_formats: true if RGBXXX output formats conflict with * each other. + * @fixed_clksrc: true if clock source is fixed * @layers: a layer description table describing available layers * @nlayers: layer description table size */ @@ -340,6 +341,7 @@ struct atmel_hlcdc_dc_desc { int max_vpw; int max_hpw; bool conflicting_output_formats; + bool fixed_clksrc; const struct atmel_hlcdc_layer_desc *layers; int nlayers; };