From patchwork Tue Apr 17 13:38:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Fabrice Gasnier X-Patchwork-Id: 899299 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=st.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40QRHt1Pyjz9s0x for ; Tue, 17 Apr 2018 23:42:02 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753599AbeDQNld (ORCPT ); Tue, 17 Apr 2018 09:41:33 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:11320 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753384AbeDQNjl (ORCPT ); Tue, 17 Apr 2018 09:39:41 -0400 Received: from pps.filterd (m0046668.ppops.net [127.0.0.1]) by mx07-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w3HDcpwE021177; Tue, 17 Apr 2018 15:39:05 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com with ESMTP id 2hbd6cy2uv-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Tue, 17 Apr 2018 15:39:05 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id DE4A241; Tue, 17 Apr 2018 13:39:03 +0000 (GMT) Received: from Webmail-eu.st.com (gpxdag5node6.st.com [10.75.127.79]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id BC8824ECE; Tue, 17 Apr 2018 13:39:03 +0000 (GMT) Received: from localhost (10.75.127.121) by GPXDAG5NODE6.st.com (10.75.127.79) with Microsoft SMTP Server (TLS) id 15.0.1347.2; Tue, 17 Apr 2018 15:39:03 +0200 From: Fabrice Gasnier To: , CC: , , , , , , , , , , , , Subject: [PATCH v5 4/6] pwm: stm32: improve capture by tuning counter prescaler Date: Tue, 17 Apr 2018 15:38:31 +0200 Message-ID: <1523972313-28765-5-git-send-email-fabrice.gasnier@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1523972313-28765-1-git-send-email-fabrice.gasnier@st.com> References: <1523972313-28765-1-git-send-email-fabrice.gasnier@st.com> MIME-Version: 1.0 X-Originating-IP: [10.75.127.121] X-ClientProxiedBy: GPXDAG4NODE6.st.com (10.75.127.76) To GPXDAG5NODE6.st.com (10.75.127.79) X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-04-17_07:, , signatures=0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Currently, capture is based on timeout window to configure prescaler. PWM capture framework provides 1s window at the time of writing. There's place for improvement, after input signal has been captured once: - Finer tune counter clock prescaler, by using 1st capture result (with arbitrary margin). - Do a 2nd capture, with scaled capture window. This increases accuracy, especially at high rates. Signed-off-by: Fabrice Gasnier Reviewed-by: Benjamin Gaignard Acked-by: Thierry Reding --- Changes in v2: - Adopt DMA read from MFD core. --- drivers/pwm/pwm-stm32.c | 24 +++++++++++++++++++++++- 1 file changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-stm32.c b/drivers/pwm/pwm-stm32.c index ed3961b..9a50acd 100644 --- a/drivers/pwm/pwm-stm32.c +++ b/drivers/pwm/pwm-stm32.c @@ -168,7 +168,7 @@ static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm, struct stm32_pwm *priv = to_stm32_pwm_dev(chip); unsigned long long prd, div, dty; unsigned long rate; - unsigned int psc = 0; + unsigned int psc = 0, scale; u32 raw_prd, raw_dty; int ret = 0; @@ -219,6 +219,28 @@ static int stm32_pwm_capture(struct pwm_chip *chip, struct pwm_device *pwm, if (ret) goto stop; + /* + * Got a capture. Try to improve accuracy at high rates: + * - decrease counter clock prescaler, scale up to max rate. + */ + if (raw_prd) { + u32 max_arr = priv->max_arr - 0x1000; /* arbitrary margin */ + + scale = max_arr / min(max_arr, raw_prd); + } else { + scale = priv->max_arr; /* bellow resolution, use max scale */ + } + + if (psc && scale > 1) { + /* 2nd measure with new scale */ + psc /= scale; + regmap_write(priv->regmap, TIM_PSC, psc); + ret = stm32_pwm_raw_capture(priv, pwm, tmo_ms, &raw_prd, + &raw_dty); + if (ret) + goto stop; + } + prd = (unsigned long long)raw_prd * (psc + 1) * NSEC_PER_SEC; result->period = DIV_ROUND_UP_ULL(prd, rate); dty = (unsigned long long)raw_dty * (psc + 1) * NSEC_PER_SEC;