From patchwork Fri Feb 24 05:41:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Volkau X-Patchwork-Id: 731912 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vV0Ms6FPZz9s7t for ; Fri, 24 Feb 2017 16:41:29 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="WgGEdb3b"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751169AbdBXFl3 (ORCPT ); Fri, 24 Feb 2017 00:41:29 -0500 Received: from mail-lf0-f65.google.com ([209.85.215.65]:33911 "EHLO mail-lf0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751080AbdBXFl3 (ORCPT ); Fri, 24 Feb 2017 00:41:29 -0500 Received: by mail-lf0-f65.google.com with SMTP id h67so749503lfg.1 for ; Thu, 23 Feb 2017 21:41:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=2lvbProFnYhKa0aXS0GsYmU7m4ofgvA27WCLqn7XpqA=; b=WgGEdb3boUBGXsHe63haELYzhqzi7Y3OCgHl7Mh12gBvfY0WdQGEucRts0RD9cGW08 RGCnE7kVurmynCXTvXja79FRPO3u6m2+yk8rnGq2evjpZVamQEgiBBxvUE/pMBGXBAv7 LBVHCqPOHoJ7BN9+7P7KRA2oCRpZfjhoe02wR5wzKKnmqdDU/adN7wmaZZvKAyIS0lZ2 1ygocWDggw9SeW7x7+v+0W5BF6fFYIze2kRqCYSwUORzWQZ2QcatTeS6pCF1uTdxF8l2 7FTj+xXdT/VSzerPf5wX9r1zruQ2bJcKuOWZF8uuAV8LKHc2ZJ404my+T0Ej+1L8O9mJ K58g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=2lvbProFnYhKa0aXS0GsYmU7m4ofgvA27WCLqn7XpqA=; b=CGyBZpr33gPGHCaoYcShfGE4LcGOGRuqW6yyiiqSFaW0eZ8RqsQKcHQwcRfNPSwzsa 9wfpfbfQDzu+QTh/qeNJx9hFhlb6gly61wyYqNSWmVNSutfd9aFB7e6eJRuLnc6Vw3dN WfLl0uIUhACpwcUSbS8hXW4Lzpshclo6EIaP620L/ViKafKrQbYd/zowqUqx9v7U8BuZ sM4vz2cHbM1sUGddjFGQtcPMpP9sHH064jKevWK2aE4wRCOafqpMWQhgITcz6jeR5gYx Vjad02BXt8QHPX6eS1aq8qsg4ArAbx3LJJauqe43O3WBM4zZjlub+Z7nEMQ/SeROVfJT aNvw== X-Gm-Message-State: AMke39m5j/Y3DhumYfk0H9eFjxvxhJi2r10w0ukxkX2EMaUPjYsyGYCTOHbaua69b6sEUQ== X-Received: by 10.46.14.1 with SMTP id 1mr216659ljo.60.1487914887238; Thu, 23 Feb 2017 21:41:27 -0800 (PST) Received: from hp-envy-1014.local (mm-118-67-212-37.vitebsk.dynamic.pppoe.byfly.by. [37.212.67.118]) by smtp.gmail.com with ESMTPSA id d77sm1764975lfd.26.2017.02.23.21.41.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 Feb 2017 21:41:26 -0800 (PST) From: lis8215@gmail.com To: linux-sunxi@googlegroups.com Cc: thierry.reding@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux-pwm@vger.kernel.org, Siarhei Volkau Subject: [PATCH v4 7/9] pwm: sunxi: Add support the Allwinner A31 PWM. Date: Fri, 24 Feb 2017 08:41:14 +0300 Message-Id: <1487914876-8594-8-git-send-email-lis8215@gmail.com> X-Mailer: git-send-email 2.4.11 In-Reply-To: <1487914876-8594-1-git-send-email-lis8215@gmail.com> References: <1487914876-8594-1-git-send-email-lis8215@gmail.com> Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Siarhei Volkau This patch introduce the sun6i PWM driver itself: - sun6i channels register and field map, - sun6i prescaler table, - DT bindings for A31 SoC, - documentation update. Signed-off-by: Siarhei Volkau --- .../devicetree/bindings/pwm/pwm-sun4i.txt | 3 +- drivers/pwm/pwm-sun4i.c | 95 +++++++++++++++++++++- 2 files changed, 95 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt b/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt index f1cbeef..109b997 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-sun4i.txt @@ -1,10 +1,11 @@ -Allwinner sun4i and sun7i SoC PWM controller +Allwinner sunxi SoC PWM controller Required properties: - compatible: should be one of: - "allwinner,sun4i-a10-pwm" - "allwinner,sun5i-a10s-pwm" - "allwinner,sun5i-a13-pwm" + - "allwinner,sun6i-a31-pwm" - "allwinner,sun7i-a20-pwm" - "allwinner,sun8i-h3-pwm" - reg: physical base address and length of the controller's registers diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index a179a53..e474303 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -1,7 +1,8 @@ /* - * Driver for Allwinner sun4i Pulse Width Modulation Controller + * Driver for Allwinner sunxi Pulse Width Modulation Controller * * Copyright (C) 2014 Alexandre Belloni + * Copyright (C) 2017 Siarhei Volkau * * Licensed under GPLv2. */ @@ -48,6 +49,12 @@ #define SUNXI_MAX_PWM_CHANNELS 4 +#define SUN6I_PWMCH_OFFS 0x10 +#define SUN6I_CH_CTL_OFFS 0x0 +#define SUN6I_CH_PRD_OFFS 0x4 +#define SUN6I_PWM_CTL_REG(ch) (SUN6I_PWMCH_OFFS * (ch) + SUN6I_CH_CTL_OFFS) +#define SUN6I_PWM_PRD_REG(ch) (SUN6I_PWMCH_OFFS * (ch) + SUN6I_CH_PRD_OFFS) + /* regmap fields */ enum { /* Used bit fields in control register */ @@ -79,6 +86,25 @@ static const u32 sun4i_prescaler_table[] = { 0, /* Actually 1 but tested separately */ }; +static const u32 sun6i_prescaler_table[] = { + 1, + 2, + 4, + 8, + 16, + 32, + 64, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + struct sunxi_pwmch_data { unsigned int ctl_reg; unsigned int prd_reg; @@ -339,6 +365,54 @@ static const struct sunxi_pwmch_data sun4i_pwm_chan1_data = { }, }; +static const struct sunxi_pwmch_data sun6i_pwm_chan0_data = { + .ctl_reg = SUN6I_PWM_CTL_REG(0), + .prd_reg = SUN6I_PWM_PRD_REG(0), + .enable_bits = PWM_EN | PWM_CLK_GATING, + .fields = { + [FIELD_PRESCALER] = REG_FIELD(SUN6I_PWM_CTL_REG(0), 0, 3), + [FIELD_POLARITY] = REG_FIELD(SUN6I_PWM_CTL_REG(0), 5, 5), + [FIELD_CLK_GATING] = REG_FIELD(SUN6I_PWM_CTL_REG(0), 6, 6), + [FIELD_READY] = REG_FIELD(SUN6I_PWM_CTL_REG(0), 28, 28), + }, +}; + +static const struct sunxi_pwmch_data sun6i_pwm_chan1_data = { + .ctl_reg = SUN6I_PWM_CTL_REG(1), + .prd_reg = SUN6I_PWM_PRD_REG(1), + .enable_bits = PWM_EN | PWM_CLK_GATING, + .fields = { + [FIELD_PRESCALER] = REG_FIELD(SUN6I_PWM_CTL_REG(1), 0, 3), + [FIELD_POLARITY] = REG_FIELD(SUN6I_PWM_CTL_REG(1), 5, 5), + [FIELD_CLK_GATING] = REG_FIELD(SUN6I_PWM_CTL_REG(1), 6, 6), + [FIELD_READY] = REG_FIELD(SUN6I_PWM_CTL_REG(1), 28, 28), + }, +}; + +static const struct sunxi_pwmch_data sun6i_pwm_chan2_data = { + .ctl_reg = SUN6I_PWM_CTL_REG(2), + .prd_reg = SUN6I_PWM_PRD_REG(2), + .enable_bits = PWM_EN | PWM_CLK_GATING, + .fields = { + [FIELD_PRESCALER] = REG_FIELD(SUN6I_PWM_CTL_REG(2), 0, 3), + [FIELD_POLARITY] = REG_FIELD(SUN6I_PWM_CTL_REG(2), 5, 5), + [FIELD_CLK_GATING] = REG_FIELD(SUN6I_PWM_CTL_REG(2), 6, 6), + [FIELD_READY] = REG_FIELD(SUN6I_PWM_CTL_REG(2), 28, 28), + }, +}; + +static const struct sunxi_pwmch_data sun6i_pwm_chan3_data = { + .ctl_reg = SUN6I_PWM_CTL_REG(3), + .prd_reg = SUN6I_PWM_PRD_REG(3), + .enable_bits = PWM_EN | PWM_CLK_GATING, + .fields = { + [FIELD_PRESCALER] = REG_FIELD(SUN6I_PWM_CTL_REG(3), 0, 3), + [FIELD_POLARITY] = REG_FIELD(SUN6I_PWM_CTL_REG(3), 5, 5), + [FIELD_CLK_GATING] = REG_FIELD(SUN6I_PWM_CTL_REG(3), 6, 6), + [FIELD_READY] = REG_FIELD(SUN6I_PWM_CTL_REG(3), 28, 28), + }, +}; + static const struct sun4i_pwm_data sun4i_pwm_data_a10 = { .has_prescaler_bypass = false, .has_rdy = false, @@ -371,6 +445,19 @@ static const struct sun4i_pwm_data sun4i_pwm_data_a13 = { } }; +static const struct sun4i_pwm_data sun6i_pwm_data_a31 = { + .has_prescaler_bypass = false, + .has_rdy = true, + .npwm = 4, + .prescaler_table = sun6i_prescaler_table, + .chan_data = { + &sun6i_pwm_chan0_data, + &sun6i_pwm_chan1_data, + &sun6i_pwm_chan2_data, + &sun6i_pwm_chan3_data, + } +}; + static const struct sun4i_pwm_data sun4i_pwm_data_a20 = { .has_prescaler_bypass = true, .has_rdy = true, @@ -403,6 +490,9 @@ static const struct of_device_id sun4i_pwm_dt_ids[] = { .compatible = "allwinner,sun5i-a13-pwm", .data = &sun4i_pwm_data_a13, }, { + .compatible = "allwinner,sun6i-a31-pwm", + .data = &sun6i_pwm_data_a31, + }, { .compatible = "allwinner,sun7i-a20-pwm", .data = &sun4i_pwm_data_a20, }, { @@ -544,5 +634,6 @@ module_platform_driver(sun4i_pwm_driver); MODULE_ALIAS("platform:sun4i-pwm"); MODULE_AUTHOR("Alexandre Belloni "); -MODULE_DESCRIPTION("Allwinner sun4i PWM driver"); +MODULE_AUTHOR("Siarhei Volkau "); +MODULE_DESCRIPTION("Allwinner sunxi PWM driver"); MODULE_LICENSE("GPL v2");