From patchwork Fri Feb 24 05:41:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Volkau X-Patchwork-Id: 731910 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3vV0Mq4GFwz9s7t for ; Fri, 24 Feb 2017 16:41:27 +1100 (AEDT) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="l0p8tUne"; dkim-atps=neutral Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751158AbdBXFl1 (ORCPT ); Fri, 24 Feb 2017 00:41:27 -0500 Received: from mail-lf0-f68.google.com ([209.85.215.68]:33516 "EHLO mail-lf0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751127AbdBXFl1 (ORCPT ); Fri, 24 Feb 2017 00:41:27 -0500 Received: by mail-lf0-f68.google.com with SMTP id j2so753509lfe.0 for ; Thu, 23 Feb 2017 21:41:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=z9FmTH5uOsmIPifAwvxUA0UJ+wK9Ps323nE1vnbEN5w=; b=l0p8tUnexMBrrKaFjCKQPMYABWRKxn97qcZz1lSwVzkwQyodz6HKplVKSTE6sEfMM0 ShMRYr6PdCCMs8NCfiId9Xu5YQ9wjPv7vxfwRYALQgzrTqjftU/coTsEp2vuCHfVH+m1 QxQ7tAyGtmtNQY8npLybiwwuMR6i6ZIBRJxAgg8lLdzBUZhASVycJKU7JddiK18Y+qIY oe5G6XJ9v+Qx0URp4UfXMisbu1G3BuXyZOlF13GPNXnO1VcvZ9ZGvC5BGqqf5aRRxU3y cVE6pxqIJ8rxTf4hARF1sOUONRU7FJckJ6AXEbKIkT0foBTeIenCeHmdlHYLbItEGVEt Oyhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=z9FmTH5uOsmIPifAwvxUA0UJ+wK9Ps323nE1vnbEN5w=; b=E6YVB92rRAiWUMdPpu1bgW1DK0tAkaeuTv8OylheV/bSMdPJ53j6Fn3n9ix+wRtHNf nqd6CB4kY09hR4ekkgyU8896NFK0JsEbaiU+HVK76R4MYBlGF+pE5ahOitoAiGWCTays 47WpZvxJXZ9YimNRD21n89KhtiEmqUpc7OYi89Xq2onq2J5HmyvVRrW9P97tKe3CHs39 BpfWCrGhoBQE8OjLyqhA6JG0vEFwYXedp+Yt6hL6qoJoAgMIfhUA0hX1p3F5yFLtwh3u i2xpVzpZh5pP+SeqTLVKAb4aXiJoajK+awr/GGcfeat0CmUW7lrhqX9D1LfNU4pzd078 0Ngg== X-Gm-Message-State: AMke39murr7QXwqPeCP0s+X5wBe/yH9fEJNFD+c3Vv/SNHaKZFuMWRypu6M8zdE8t3caxw== X-Received: by 10.46.69.139 with SMTP id s133mr218862lja.56.1487914884958; Thu, 23 Feb 2017 21:41:24 -0800 (PST) Received: from hp-envy-1014.local (mm-118-67-212-37.vitebsk.dynamic.pppoe.byfly.by. [37.212.67.118]) by smtp.gmail.com with ESMTPSA id d77sm1764975lfd.26.2017.02.23.21.41.23 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 23 Feb 2017 21:41:24 -0800 (PST) From: lis8215@gmail.com To: linux-sunxi@googlegroups.com Cc: thierry.reding@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux-pwm@vger.kernel.org, Siarhei Volkau Subject: [PATCH v4 5/9] pwm: sunxi: Customizable regmap fields and enable bit mask. Date: Fri, 24 Feb 2017 08:41:12 +0300 Message-Id: <1487914876-8594-6-git-send-email-lis8215@gmail.com> X-Mailer: git-send-email 2.4.11 In-Reply-To: <1487914876-8594-1-git-send-email-lis8215@gmail.com> References: <1487914876-8594-1-git-send-email-lis8215@gmail.com> Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Siarhei Volkau sun6i has similar control registers bit map in comparison to sun4i channel 0, but each channel has its own control register. This patch make: - regmap fields declarations selectable, - enable/disable bitmask selectable. These things needed for support sun6i in next patches. Signed-off-by: Siarhei Volkau --- drivers/pwm/pwm-sun4i.c | 43 +++++++++++++++++++++---------------------- 1 file changed, 21 insertions(+), 22 deletions(-) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index 9ddc812..9463148 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -82,6 +82,8 @@ static const u32 sun4i_prescaler_table[] = { struct sunxi_pwmch_data { unsigned int ctl_reg; unsigned int prd_reg; + u32 enable_bits; + struct reg_field fields[NUM_FIELDS]; }; struct sun4i_pwm_data { @@ -271,8 +273,7 @@ static int sun4i_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) return ret; } - mask = BIT_CH(PWM_EN, pwm->hwpwm); - mask |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm); + mask = sun4i_pwm->data->chan_data[pwm->hwpwm]->enable_bits; spin_lock(&sun4i_pwm->ctrl_lock); ret = regmap_update_bits(sun4i_pwm->regmap, @@ -293,8 +294,7 @@ static void sun4i_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) u32 mask; int err; - mask = BIT_CH(PWM_EN, pwm->hwpwm); - mask |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm); + mask = sun4i_pwm->data->chan_data[pwm->hwpwm]->enable_bits; spin_lock(&sun4i_pwm->ctrl_lock); err = regmap_update_bits(sun4i_pwm->regmap, @@ -315,30 +315,28 @@ static const struct pwm_ops sun4i_pwm_ops = { .owner = THIS_MODULE, }; -static const struct reg_field -sun4i_pwm_regfields[SUN4I_MAX_PWM_CHANNELS][NUM_FIELDS] = { - { +static const struct sunxi_pwmch_data sun4i_pwm_chan0_data = { + .ctl_reg = PWM_CTRL_REG, + .prd_reg = PWM_CH_PRD(0), + .enable_bits = BIT_CH(PWM_EN | PWM_CLK_GATING, 0), + .fields = { [FIELD_PRESCALER] = REG_FIELD(PWM_CTRL_REG, 0, 3), [FIELD_POLARITY] = REG_FIELD(PWM_CTRL_REG, 5, 5), [FIELD_CLK_GATING] = REG_FIELD(PWM_CTRL_REG, 6, 6), [FIELD_READY] = REG_FIELD(PWM_CTRL_REG, 28, 28), }, - { - [FIELD_PRESCALER] = REG_FIELD(PWM_CTRL_REG, 15, 18), - [FIELD_POLARITY] = REG_FIELD(PWM_CTRL_REG, 20, 20), - [FIELD_CLK_GATING] = REG_FIELD(PWM_CTRL_REG, 21, 21), - [FIELD_READY] = REG_FIELD(PWM_CTRL_REG, 29, 29), - }, -}; - -static const struct sunxi_pwmch_data sun4i_pwm_chan0_data = { - .ctl_reg = PWM_CTRL_REG, - .prd_reg = PWM_CH_PRD(0), }; static const struct sunxi_pwmch_data sun4i_pwm_chan1_data = { .ctl_reg = PWM_CTRL_REG, .prd_reg = PWM_CH_PRD(1), + .enable_bits = BIT_CH(PWM_EN | PWM_CLK_GATING, 1), + .fields = { + [FIELD_PRESCALER] = REG_FIELD(PWM_CTRL_REG, 15, 18), + [FIELD_POLARITY] = REG_FIELD(PWM_CTRL_REG, 20, 20), + [FIELD_CLK_GATING] = REG_FIELD(PWM_CTRL_REG, 21, 21), + [FIELD_READY] = REG_FIELD(PWM_CTRL_REG, 29, 29), + }, }; static const struct sun4i_pwm_data sun4i_pwm_data_a10 = { @@ -422,17 +420,18 @@ static const struct regmap_config sunxi_pwm_regmap_config = { .reg_stride = 4, }; -static int sun4i_alloc_reg_fields(struct device *dev, +static int sunxi_alloc_reg_fields(struct device *dev, struct sun4i_pwm_chip *pwm, int chan) { int i, err; + const struct sunxi_pwmch_data *data = pwm->data->chan_data[chan]; - if (chan >= SUN4I_MAX_PWM_CHANNELS) + if (!data || chan >= SUN4I_MAX_PWM_CHANNELS) return -EINVAL; for (i = 0; i < NUM_FIELDS; i++) { pwm->fields[chan][i] = devm_regmap_field_alloc(dev, pwm->regmap, - sun4i_pwm_regfields[chan][i]); + data->fields[i]); if (IS_ERR(pwm->fields[chan][i])) { dev_err(dev, "regmap field allocation failed\n"); err = PTR_ERR(pwm->fields[chan][i]); @@ -499,7 +498,7 @@ static int sun4i_pwm_probe(struct platform_device *pdev) } for (i = 0; i < pwm->chip.npwm; i++) { - ret = sun4i_alloc_reg_fields(&pdev->dev, pwm, i); + ret = sunxi_alloc_reg_fields(&pdev->dev, pwm, i); if (ret) goto read_error; }