From patchwork Wed Jun 22 11:47:22 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laxman Dewangan X-Patchwork-Id: 639129 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3rZNVp6l2Rz9t1H for ; Wed, 22 Jun 2016 22:01:54 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752646AbcFVMBV (ORCPT ); Wed, 22 Jun 2016 08:01:21 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:14495 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752683AbcFVMBS (ORCPT ); Wed, 22 Jun 2016 08:01:18 -0400 Received: from hqnvupgp07.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Wed, 22 Jun 2016 05:00:52 -0700 Received: from HQHUB101.nvidia.com ([172.20.187.24]) by hqnvupgp07.nvidia.com (PGP Universal service); Wed, 22 Jun 2016 05:00:34 -0700 X-PGP-Universal: processed; by hqnvupgp07.nvidia.com on Wed, 22 Jun 2016 05:00:34 -0700 Received: from BGMAIL102.nvidia.com (10.25.59.11) by HQHUB101.nvidia.com (172.20.187.24) with Microsoft SMTP Server (TLS) id 8.3.406.0; Wed, 22 Jun 2016 05:01:16 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by bgmail102.nvidia.com (10.25.59.11) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Wed, 22 Jun 2016 12:01:12 +0000 Received: from ldewanganubuntu-System-Product-Name.nvidia.com (172.20.13.39) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Wed, 22 Jun 2016 12:01:09 +0000 From: Laxman Dewangan To: , , , CC: , , , , Laxman Dewangan Subject: [PATCH 4/5] pwm: tegra: Add DT node compatible for Tegra186 Date: Wed, 22 Jun 2016 17:17:22 +0530 Message-ID: <1466596043-27262-5-git-send-email-ldewangan@nvidia.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1466596043-27262-1-git-send-email-ldewangan@nvidia.com> References: <1466596043-27262-1-git-send-email-ldewangan@nvidia.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Tegra186 has 8 different PWM controller and each controller has only one output. Earlier generation SoCs have the 4 PWM output per controller. Add DT node compatible for Tegra186. Signed-off-by: Laxman Dewangan --- Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt index c52f03b..2851b2d 100644 --- a/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt +++ b/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt @@ -1,10 +1,12 @@ Tegra SoC PWFM controller Required properties: -- compatible: For Tegra20, must contain "nvidia,tegra20-pwm". For Tegra30, - must contain "nvidia,tegra30-pwm". Otherwise, must contain - "nvidia,-pwm", plus one of the above, where is tegra114, - tegra124, tegra132, or tegra210. +- compatible: For Tegra20, must contain "nvidia,tegra20-pwm". + For Tegra30, must contain "nvidia,tegra30-pwm". + For Tegra114, Tegra124, Tegra132, Tegra210 must contain + "nvidia,-pwm", plus one of the above, where is + tegra114, tegra124, tegra132, or tegra210. + For Tegra186, must contain "nvidia,tegra186-pwm". - reg: physical base address and length of the controller's registers - #pwm-cells: should be 2. See pwm.txt in this directory for a description of the cells format.