From patchwork Fri Apr 22 10:31:09 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Penny Chiu X-Patchwork-Id: 613519 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3qrsRQ3CMcz9t3s for ; Fri, 22 Apr 2016 20:33:54 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752053AbcDVKdk (ORCPT ); Fri, 22 Apr 2016 06:33:40 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:4610 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752809AbcDVKcm (ORCPT ); Fri, 22 Apr 2016 06:32:42 -0400 Received: from hqnvupgp08.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com id ; Fri, 22 Apr 2016 03:32:34 -0700 Received: from HQMAIL108.nvidia.com ([172.18.146.13]) by hqnvupgp08.nvidia.com (PGP Universal service); Fri, 22 Apr 2016 03:32:30 -0700 X-PGP-Universal: processed; by hqnvupgp08.nvidia.com on Fri, 22 Apr 2016 03:32:30 -0700 Received: from HQMAIL106.nvidia.com (172.18.146.12) by HQMAIL108.nvidia.com (172.18.146.13) with Microsoft SMTP Server (TLS) id 15.0.1130.7; Fri, 22 Apr 2016 10:32:40 +0000 Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL106.nvidia.com (172.18.146.12) with Microsoft SMTP Server id 15.0.1130.7 via Frontend Transport; Fri, 22 Apr 2016 10:32:40 +0000 Received: from pchiu-i7.nvidia.com (Not Verified[10.19.120.104]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7, 5, 5, 8150) id ; Fri, 22 Apr 2016 03:32:41 -0700 From: Penny Chiu To: , , , , , , CC: , , , , , , , , Penny Chiu Subject: [PATCH 09/11] arm64: tegra: Add DFLL clock node on Jetson TX1 Date: Fri, 22 Apr 2016 18:31:09 +0800 Message-ID: <1461321071-6431-10-git-send-email-pchiu@nvidia.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1461321071-6431-1-git-send-email-pchiu@nvidia.com> References: <1461321071-6431-1-git-send-email-pchiu@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Add DFLL clock device-tree node for Tegra210 DFLL IP block. Signed-off-by: Penny Chiu --- arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 16 ++++++++++++++++ arch/arm64/boot/dts/nvidia/tegra210.dtsi | 15 +++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi index 9d02db2..5cf07f2 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi @@ -43,6 +43,22 @@ }; }; + dfll: clock@70110000 { + status = "okay"; + + reg = <0x0 0x70110000 0x0 0x400>; + vdd-cpu-supply = <&cpu_ovr_reg>; + nvidia,pwm-to-pmic; + nvidia,init-uv = <1000000>; + nvidia,align-step-uv = <19200>; /* 19.2mv */ + nvidia,sample-rate = <25000>; + nvidia,droop-ctrl = <0x00000f00>; + nvidia,force-mode = <1>; + nvidia,cf = <6>; + nvidia,ci = <0>; + nvidia,cg = <2>; + }; + pwm_dfll: pwm@70110000 { compatible = "nvidia,tegra210-dfll-pwm"; reg = <0x0 0x70110000 0x0 0x400>; diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi index ba0462e..204d9cd 100644 --- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi +++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi @@ -3,6 +3,7 @@ #include #include #include +#include / { compatible = "nvidia,tegra210"; @@ -684,6 +685,20 @@ status = "disabled"; }; + dfll: clock@70110000 { + compatible = "nvidia,tegra210-dfll"; + interrupts = ; + clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>, + <&tegra_car TEGRA210_CLK_DFLL_REF>, + <&tegra_car TEGRA210_CLK_I2C5>; + clock-names = "soc", "ref", "i2c"; + resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>; + reset-names = "dvco"; + #clock-cells = <0>; + clock-output-names = "dfllCPU_out"; + status = "disabled"; + }; + usb@7d000000 { compatible = "nvidia,tegra210-ehci", "nvidia,tegra30-ehci", "usb-ehci"; reg = <0x0 0x7d000000 0x0 0x4000>;