From patchwork Tue Aug 18 07:27:55 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: YH Huang X-Patchwork-Id: 508198 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 11CA6140549 for ; Tue, 18 Aug 2015 17:29:21 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751778AbbHRH3C (ORCPT ); Tue, 18 Aug 2015 03:29:02 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:49583 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1751652AbbHRH2r (ORCPT ); Tue, 18 Aug 2015 03:28:47 -0400 X-Listener-Flag: 11101 Received: from mtkhts07.mediatek.inc [(172.21.101.69)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 253543709; Tue, 18 Aug 2015 15:28:39 +0800 Received: from mtkslt302.mediatek.inc (10.21.14.115) by mtkhts07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.181.6; Tue, 18 Aug 2015 15:28:38 +0800 From: YH Huang To: Matthias Brugger , Mark Rutland , Thierry Reding CC: Rob Herring , Pawel Moll , , , , , , , Sascha Hauer , , YH Huang Subject: [PATCH v7 3/3] arm64: dts: mt8173: add MT8173 display PWM driver support node Date: Tue, 18 Aug 2015 15:27:55 +0800 Message-ID: <1439882875-19596-4-git-send-email-yh.huang@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1439882875-19596-1-git-send-email-yh.huang@mediatek.com> References: <1439882875-19596-1-git-send-email-yh.huang@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Add display PWM node in mt8173-evb.dts and mt8173.dtsi. Signed-off-by: YH Huang --- arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 13 +++++++++++++ arch/arm64/boot/dts/mediatek/mt8173.dtsi | 22 ++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index 4be66ca..de95cf3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -92,6 +92,13 @@ }; &pio { + disp_pwm0_pins: disp_pwm0_pins { + pins1 { + pinmux = ; + output-low; + }; + }; + mmc0_pins_default: mmc0default { pins_cmd_dat { pinmux = , @@ -190,6 +197,12 @@ }; }; +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&disp_pwm0_pins>; + status = "okay"; +}; + &pwrap { pmic: mt6397 { compatible = "mediatek,mt6397"; diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 6c3f047..68b1ef0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -501,6 +501,28 @@ #clock-cells = <1>; }; + pwm0: pwm@1401e000 { + compatible = "mediatek,mt8173-disp-pwm", + "mediatek,mt6595-disp-pwm"; + reg = <0 0x1401e000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&mmsys CLK_MM_DISP_PWM026M>, + <&mmsys CLK_MM_DISP_PWM0MM>; + clock-names = "main", "mm"; + status = "disabled"; + }; + + pwm1: pwm@1401f000 { + compatible = "mediatek,mt8173-disp-pwm", + "mediatek,mt6595-disp-pwm"; + reg = <0 0x1401f000 0 0x1000>; + #pwm-cells = <2>; + clocks = <&mmsys CLK_MM_DISP_PWM126M>, + <&mmsys CLK_MM_DISP_PWM1MM>; + clock-names = "main", "mm"; + status = "disabled"; + }; + imgsys: clock-controller@15000000 { compatible = "mediatek,mt8173-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>;