From patchwork Fri Apr 10 18:58:52 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Richardson X-Patchwork-Id: 460192 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 5295D14009B for ; Sat, 11 Apr 2015 04:57:48 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754386AbbDJS4q (ORCPT ); Fri, 10 Apr 2015 14:56:46 -0400 Received: from mail-gw1-out.broadcom.com ([216.31.210.62]:5493 "EHLO mail-gw1-out.broadcom.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752919AbbDJS4m (ORCPT ); Fri, 10 Apr 2015 14:56:42 -0400 X-IronPort-AV: E=Sophos;i="5.11,558,1422950400"; d="scan'208";a="61970188" Received: from irvexchcas08.broadcom.com (HELO IRVEXCHCAS08.corp.ad.broadcom.com) ([10.9.208.57]) by mail-gw1-out.broadcom.com with ESMTP; 10 Apr 2015 12:15:04 -0700 Received: from IRVEXCHSMTP3.corp.ad.broadcom.com (10.9.207.53) by IRVEXCHCAS08.corp.ad.broadcom.com (10.9.208.57) with Microsoft SMTP Server (TLS) id 14.3.174.1; Fri, 10 Apr 2015 11:56:40 -0700 Received: from mail-irva-13.broadcom.com (10.10.10.20) by IRVEXCHSMTP3.corp.ad.broadcom.com (10.9.207.53) with Microsoft SMTP Server id 14.3.174.1; Fri, 10 Apr 2015 11:56:39 -0700 Received: from lbrmn-lnxub108.corp.ad.broadcom.com (unknown [10.136.4.151]) by mail-irva-13.broadcom.com (Postfix) with ESMTP id 45AEE40FE9; Fri, 10 Apr 2015 11:55:12 -0700 (PDT) From: Jonathan Richardson To: Tim Kryger , Dmitry Torokhov , Anatol Pomazau , Arun Ramamurthy , Thierry Reding CC: Scott Branden , Jonathan Richardson , bcm-kernel-feedback-list , , Subject: [PATCH v6 3/4] pwm: kona: Fix incorrect config, disable, and polarity procedures Date: Fri, 10 Apr 2015 11:58:52 -0700 Message-ID: <1428692333-14400-4-git-send-email-jonathar@broadcom.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1428692333-14400-1-git-send-email-jonathar@broadcom.com> References: <1428692333-14400-1-git-send-email-jonathar@broadcom.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org The config procedure didn't follow the spec which periodically resulted in failing to enable the output signal. This happened one in ten or twenty attempts. Following the spec and adding a 400ns delay in the appropriate locations resolves this problem. The disable procedure now also follows the spec. The old disable procedure would result in no change in signal when called. The polarity procedure no longer applies the settings to change the output signal because it can't be called when the pwm is enabled anyway. The polarity is only updated in the control register. The correct polarity will be applied on enable. The old method of applying changes would result in no signal when the polarity was changed. The new apply_settings function would fix this problem but it isn't required anyway. Reviewed-by: Arun Ramamurthy Reviewed-by: Scott Branden Tested-by: Scott Branden Signed-off-by: Jonathan Richardson --- drivers/pwm/pwm-bcm-kona.c | 75 +++++++++++++++++++++++++++++++++++--------- 1 file changed, 60 insertions(+), 15 deletions(-) diff --git a/drivers/pwm/pwm-bcm-kona.c b/drivers/pwm/pwm-bcm-kona.c index 32b3ec6..8a1dfba 100644 --- a/drivers/pwm/pwm-bcm-kona.c +++ b/drivers/pwm/pwm-bcm-kona.c @@ -80,15 +80,19 @@ static void kona_pwmc_apply_settings(struct kona_pwmc *kp, unsigned int chan) { unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET); - /* Clear trigger bit but set smooth bit to maintain old output */ - value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan); - value &= ~(1 << PWM_CONTROL_TRIGGER_SHIFT(chan)); - writel(value, kp->base + PWM_CONTROL_OFFSET); + /* + * There must be a min 400ns delay between clearing enable and setting + * it. Failing to do this may result in no PWM signal. + */ + ndelay(400); /* Set trigger bit and clear smooth bit to apply new settings */ value &= ~(1 << PWM_CONTROL_SMOOTH_SHIFT(chan)); value |= 1 << PWM_CONTROL_TRIGGER_SHIFT(chan); writel(value, kp->base + PWM_CONTROL_OFFSET); + + /* PWMOUT_ENABLE must be held high for at least 400 ns. */ + ndelay(400); } static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm, @@ -121,20 +125,56 @@ static int kona_pwmc_config(struct pwm_chip *chip, struct pwm_device *pwm, dc = div64_u64(val, div); /* If duty_ns or period_ns are not achievable then return */ - if (pc < PERIOD_COUNT_MIN || dc < DUTY_CYCLE_HIGH_MIN) + if (pc < PERIOD_COUNT_MIN) { + dev_warn(chip->dev, + "%s: pwm[%d]: period=%d is not achievable, pc=%lu, prescale=%lu\n", + __func__, chan, period_ns, pc, prescale); + return -EINVAL; + } + + /* If duty_ns is not achievable then return */ + if (dc < DUTY_CYCLE_HIGH_MIN) { + if (0 != duty_ns) { + dev_warn(chip->dev, + "%s: pwm[%d]: duty cycle=%d is not achievable, dc=%lu, prescale=%lu\n", + __func__, chan, duty_ns, dc, prescale); + } return -EINVAL; + } /* If pc and dc are in bounds, the calculation is done */ if (pc <= PERIOD_COUNT_MAX && dc <= DUTY_CYCLE_HIGH_MAX) break; /* Otherwise, increase prescale and recalculate pc and dc */ - if (++prescale > PRESCALE_MAX) + if (++prescale > PRESCALE_MAX) { + dev_warn(chip->dev, + "%s: pwm[%d]: Prescale (=%lu) within max (=%d) for period=%d and duty cycle=%d is not achievable\n", + __func__, chan, prescale, PRESCALE_MAX, + period_ns, duty_ns); return -EINVAL; + } } - /* If the PWM channel is enabled, write the settings to the HW */ + dev_dbg(chip->dev, "pwm[%d]: period=%lu, duty_high=%lu, prescale=%lu\n", + chan, pc, dc, prescale); + + /* + * Don't apply settings if disabled. The period and duty cycle are + * always calculated above to ensure the new values are + * validated immediately instead of on enable. + */ if (test_bit(PWMF_ENABLED, &pwm->flags)) { + value = readl(kp->base + PWM_CONTROL_OFFSET); + + /* + * Clear trigger bit but set smooth bit to maintain old + * output. + */ + value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan); + value &= ~(1 << PWM_CONTROL_TRIGGER_SHIFT(chan)); + writel(value, kp->base + PWM_CONTROL_OFFSET); + value = readl(kp->base + PRESCALE_OFFSET); value &= ~PRESCALE_MASK(chan); value |= prescale << PRESCALE_SHIFT(chan); @@ -173,11 +213,6 @@ static int kona_pwmc_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm, writel(value, kp->base + PWM_CONTROL_OFFSET); - kona_pwmc_apply_settings(kp, chan); - - /* Wait for waveform to settle before gating off the clock */ - ndelay(400); - clk_disable_unprepare(kp->clk); return 0; @@ -207,13 +242,23 @@ static void kona_pwmc_disable(struct pwm_chip *chip, struct pwm_device *pwm) { struct kona_pwmc *kp = to_kona_pwmc(chip); unsigned int chan = pwm->hwpwm; + unsigned int value = readl(kp->base + PWM_CONTROL_OFFSET); + + /* Set smooth type to 1 and disable */ + value |= 1 << PWM_CONTROL_SMOOTH_SHIFT(chan); + value &= ~(1 << PWM_CONTROL_TRIGGER_SHIFT(chan)); + writel(value, kp->base + PWM_CONTROL_OFFSET); /* Simulate a disable by configuring for zero duty */ writel(0, kp->base + DUTY_CYCLE_HIGH_OFFSET(chan)); - kona_pwmc_apply_settings(kp, chan); + writel(0, kp->base + PERIOD_COUNT_OFFSET(chan)); - /* Wait for waveform to settle before gating off the clock */ - ndelay(400); + /* Set prescale to 0 for this channel */ + value = readl(kp->base + PRESCALE_OFFSET); + value &= ~PRESCALE_MASK(chan); + writel(value, kp->base + PRESCALE_OFFSET); + + kona_pwmc_apply_settings(kp, chan); clk_disable_unprepare(kp->clk); }