| Message ID | 1412676860-12120-3-git-send-email-boris.brezillon@free-electrons.com |
|---|---|
| State | Superseded |
| Headers | show |
On 07/10/2014 12:14, Boris Brezillon : > The HLCDC IP available in some Atmel SoCs (i.e. sam9x5i.e. at91sam9n12, Ditto: sam9x5 doesn't exist. > at91sam9x5 family or sama5d3 family) provide a PWM device. > > The DT bindings used for this PWM device is following the default 3 cells > bindings described in Documentation/devicetree/bindings/pwm/pwm.txt. > > Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> > --- > .../devicetree/bindings/pwm/atmel-hlcdc-pwm.txt | 29 ++++++++++++++++++++++ > 1 file changed, 29 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt > > diff --git a/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt b/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt > new file mode 100644 > index 0000000..8a85244 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt > @@ -0,0 +1,29 @@ > +Device-Tree bindings for Atmel's HLCDC (High LCD Controller) PWM driver s/High/High-end/ > + > +The Atmel HLCDC PWM is subdevice of the HLCDC MFD device. > +See ../mfd/atmel-hlcdc.txt for more details. > + > +Required properties: > + - compatible: value should be one of the following: > + "atmel,hlcdc-pwm" > + - pinctr-names: the pin control state names. Should contain "default". > + - pinctrl-0: should contain the pinctrl states described by pinctrl > + default. > + - #pwm-cells: should be set to 3. This PWM chip use the default 3 cells > + bindings defined in pwm.txt in this directory. > + > +Example: > + > + hlcdc: hlcdc@f0030000 { > + compatible = "atmel,sama5d3-hlcdc"; > + reg = <0xf0030000 0x2000>; > + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; > + clock-names = "periph_clk","sys_clk", "slow_clk"; > + > + hlcdc_pwm: hlcdc-pwm { > + > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_lcd_pwm>; > + #pwm-cells = <3>; > + }; > + }; > otherwise, Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Thanks.
diff --git a/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt b/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt new file mode 100644 index 0000000..8a85244 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt @@ -0,0 +1,29 @@ +Device-Tree bindings for Atmel's HLCDC (High LCD Controller) PWM driver + +The Atmel HLCDC PWM is subdevice of the HLCDC MFD device. +See ../mfd/atmel-hlcdc.txt for more details. + +Required properties: + - compatible: value should be one of the following: + "atmel,hlcdc-pwm" + - pinctr-names: the pin control state names. Should contain "default". + - pinctrl-0: should contain the pinctrl states described by pinctrl + default. + - #pwm-cells: should be set to 3. This PWM chip use the default 3 cells + bindings defined in pwm.txt in this directory. + +Example: + + hlcdc: hlcdc@f0030000 { + compatible = "atmel,sama5d3-hlcdc"; + reg = <0xf0030000 0x2000>; + clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>; + clock-names = "periph_clk","sys_clk", "slow_clk"; + + hlcdc_pwm: hlcdc-pwm { + compatible = "atmel,hlcdc-pwm"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd_pwm>; + #pwm-cells = <3>; + }; + };
The HLCDC IP available in some Atmel SoCs (i.e. sam9x5i.e. at91sam9n12, at91sam9x5 family or sama5d3 family) provide a PWM device. The DT bindings used for this PWM device is following the default 3 cells bindings described in Documentation/devicetree/bindings/pwm/pwm.txt. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> --- .../devicetree/bindings/pwm/atmel-hlcdc-pwm.txt | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/atmel-hlcdc-pwm.txt