From patchwork Wed Jul 16 01:55:13 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Huayi Li X-Patchwork-Id: 370581 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id C359214011E for ; Wed, 16 Jul 2014 13:05:07 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1760613AbaGPDEt (ORCPT ); Tue, 15 Jul 2014 23:04:49 -0400 Received: from cluster-g.mailcontrol.com ([208.87.233.190]:34793 "EHLO cluster-g.mailcontrol.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760605AbaGPDEr (ORCPT ); Tue, 15 Jul 2014 23:04:47 -0400 Received: from shaapppus01.asia.root.pri ([210.13.83.99]) by rly08g.srv.mailcontrol.com (MailControl) with ESMTP id s6G1uaZD046082 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=NO); Wed, 16 Jul 2014 02:56:38 +0100 Received: from shaasiexc01.ASIA.ROOT.PRI ([10.125.12.102]) by shaapppus01.asia.root.pri (PGP Universal service); Wed, 16 Jul 2014 09:56:39 +0800 X-PGP-Universal: processed; by shaapppus01.asia.root.pri on Wed, 16 Jul 2014 09:56:39 +0800 Received: from shaunxand01.ASIA.ROOT.PRI (10.125.12.180) by asimail.csr.com (10.125.12.88) with Microsoft SMTP Server (TLS) id 14.3.158.1; Wed, 16 Jul 2014 09:56:35 +0800 From: Huayi Li To: Thierry Reding , , Grant Likely , Rob Herring , , CC: , , , , Huayi Li Subject: [PATCH v5 3/4] ARM: dts: sirf: fix the pwm-cells and clocks Date: Wed, 16 Jul 2014 09:55:13 +0800 Message-ID: <1405475714-10006-4-git-send-email-huayi.li@csr.com> X-Mailer: git-send-email 1.9.3 In-Reply-To: <1405475714-10006-1-git-send-email-huayi.li@csr.com> References: <1405475714-10006-1-git-send-email-huayi.li@csr.com> MIME-Version: 1.0 X-Originating-IP: [10.125.12.180] X-CFilter-Loop: Reflected X-Scanned-By: MailControl 30291.32 (www.mailcontrol.com) on 10.71.0.118 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This patch adds missed pwm-cells, clock-names and signal source clock for PWM module. Signed-off-by: Huayi Li Reviewed-by: Barry Song --- arch/arm/boot/dts/atlas6.dtsi | 8 ++++++-- arch/arm/boot/dts/prima2.dtsi | 8 ++++++-- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/atlas6.dtsi b/arch/arm/boot/dts/atlas6.dtsi index bb22842..d424a69 100644 --- a/arch/arm/boot/dts/atlas6.dtsi +++ b/arch/arm/boot/dts/atlas6.dtsi @@ -638,10 +638,14 @@ }; }; - pwm@b0130000 { + pwm: pwm@b0130000 { compatible = "sirf,prima2-pwm"; + #pwm-cells = <2>; reg = <0xb0130000 0x10000>; - clocks = <&clks 21>; + clocks = <&clks 21>, <&clks 1>, <&clks 2>, + <&clks 3>, <&clks 0>, <&clks 4>; + clock-names = "pwmc", "sigsrc0", "sigsrc1", + "sigsrc2", "sigsrc3", "sigsrc4"; }; efusesys@b0140000 { diff --git a/arch/arm/boot/dts/prima2.dtsi b/arch/arm/boot/dts/prima2.dtsi index 963b7e5..68bb0c4 100644 --- a/arch/arm/boot/dts/prima2.dtsi +++ b/arch/arm/boot/dts/prima2.dtsi @@ -646,10 +646,14 @@ }; }; - pwm@b0130000 { + pwm: pwm@b0130000 { compatible = "sirf,prima2-pwm"; + #pwm-cells = <2>; reg = <0xb0130000 0x10000>; - clocks = <&clks 21>; + clocks = <&clks 21>, <&clks 1>, <&clks 2>, + <&clks 3>, <&clks 0>, <&clks 4>; + clock-names = "pwmc", "sigsrc0", "sigsrc1", + "sigsrc2", "sigsrc3", "sigsrc4"; }; efusesys@b0140000 {