From patchwork Wed May 7 23:08:35 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Beniamino Galvani X-Patchwork-Id: 346845 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 1428A1401B1 for ; Thu, 8 May 2014 09:10:24 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752088AbaEGXKG (ORCPT ); Wed, 7 May 2014 19:10:06 -0400 Received: from mail-ee0-f49.google.com ([74.125.83.49]:40588 "EHLO mail-ee0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751769AbaEGXJu (ORCPT ); Wed, 7 May 2014 19:09:50 -0400 Received: by mail-ee0-f49.google.com with SMTP id e53so1161033eek.8 for ; Wed, 07 May 2014 16:09:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=3Ch86sP4iSdJ7QWlv8nu+7Ih6CZ2MCh9kSXnRs0+yzg=; b=QIEszmosBZXsY4uioUs4mraTJ70VewAWBhoK2hWBa78sflmLVo5MB5y+NblE06+y/n cyrHDn9BiNwmT2fslorGPD/OZaU8w8d740fejw2fArOTLEw3LpkUKMBeX8ebS/nwmeI7 D74P8Mrm2G+YuMnmHgcgAWEOCyA64MNDZIlC3qQTzLd0WefeZOxW1XVHdL7yENlckTJ4 feXpRtFxFK1IECOSKm1k7ZPZ2QkIUpkLjtkxNxHN6Q9CQsU8/WLThpRZUKyVVDPm6vIs +YyGNOfo8kpLIJr2R85KBtB2nstNpeEN+wsU0k8mAM2VTrDQiKFHWcRNDPYsRa4vJqmu OFOA== X-Received: by 10.14.100.69 with SMTP id y45mr581625eef.108.1399504188706; Wed, 07 May 2014 16:09:48 -0700 (PDT) Received: from sark.local (host214-92-dynamic.1-79-r.retail.telecomitalia.it. [79.1.92.214]) by mx.google.com with ESMTPSA id u1sm133214eex.31.2014.05.07.16.09.46 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 07 May 2014 16:09:48 -0700 (PDT) From: Beniamino Galvani To: Thierry Reding Cc: Heiko Stuebner , linux-pwm@vger.kernel.org, Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Randy Dunlap , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Beniamino Galvani Subject: [PATCH 3/3] ARM: dts: rk3xxx: add PWM nodes Date: Thu, 8 May 2014 01:08:35 +0200 Message-Id: <1399504115-16257-4-git-send-email-b.galvani@gmail.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1399504115-16257-1-git-send-email-b.galvani@gmail.com> References: <1399504115-16257-1-git-send-email-b.galvani@gmail.com> Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This adds PWM nodes to the Rockchip device trees. Signed-off-by: Beniamino Galvani --- arch/arm/boot/dts/rk3188.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/rk3xxx.dtsi | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 72 insertions(+) diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi index f1d8651..7dd8f6c 100644 --- a/arch/arm/boot/dts/rk3188.dtsi +++ b/arch/arm/boot/dts/rk3188.dtsi @@ -125,6 +125,22 @@ clock-names = "biu", "ciu"; }; + pwm0: pwm@20030000 { + clocks = <&cru PCLK_PWM01>; + }; + + pwm1: pwm@20030010 { + clocks = <&cru PCLK_PWM01>; + }; + + pwm2: pwm@20050020 { + clocks = <&cru PCLK_PWM23>; + }; + + pwm3: pwm@20050030 { + clocks = <&cru PCLK_PWM23>; + }; + cru: cru@20000000 { compatible = "rockchip,rk3188-cru"; reg = <0x20000000 0x1000>, @@ -331,6 +347,30 @@ ; }; }; + + pwm0 { + pwm0_pins: pwm0-pins { + rockchip,pins = ; + }; + }; + + pwm1 { + pwm1_pins: pwm1-pins { + rockchip,pins = ; + }; + }; + + pwm2 { + pwm2_pins: pwm2-pins { + rockchip,pins = ; + }; + }; + + pwm3 { + pwm3_pins: pwm3-pins { + rockchip,pins = ; + }; + }; }; }; }; diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi index 26e5a96..c46d552 100644 --- a/arch/arm/boot/dts/rk3xxx.dtsi +++ b/arch/arm/boot/dts/rk3xxx.dtsi @@ -130,5 +130,37 @@ status = "disabled"; }; + + pwm0: pwm@20030000 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20030000 0x10>; + #pwm-cells = <2>; + clocks = <&clk_gates7 10>; + status = "disabled"; + }; + + pwm1: pwm@20030010 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20030010 0x10>; + #pwm-cells = <2>; + clocks = <&clk_gates7 10>; + status = "disabled"; + }; + + pwm2: pwm@20050020 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050020 0x10>; + #pwm-cells = <2>; + clocks = <&clk_gates7 11>; + status = "disabled"; + }; + + pwm3: pwm@20050030 { + compatible = "rockchip,rk2928-pwm"; + reg = <0x20050030 0x10>; + #pwm-cells = <2>; + clocks = <&clk_gates7 11>; + status = "disabled"; + }; }; };