@@ -1148,6 +1148,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
imx6_pcie->vph = NULL;
}
+ max_pcie_mrrs = 512;
platform_set_drvdata(pdev, imx6_pcie);
ret = imx6_pcie_attach_pd(dev);
@@ -112,6 +112,8 @@ enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_PEER2PEER;
enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
#endif
+u16 max_pcie_mrrs = 4096; // no limit
+
/*
* The default CLS is used if arch didn't set CLS explicitly and not
* all pci devices agree on the same value. Arch can override either
@@ -5816,6 +5818,9 @@ int pcie_set_readrq(struct pci_dev *dev, int rq)
rq = mps;
}
+ if (rq > max_pcie_mrrs)
+ rq = max_pcie_mrrs;
+
v = (ffs(rq) - 8) << 12;
ret = pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
@@ -996,6 +996,7 @@ enum pcie_bus_config_types {
};
extern enum pcie_bus_config_types pcie_bus_config;
+extern u16 max_pcie_mrrs;
extern struct bus_type pci_bus_type;
DWC PCIe controller imposes limits on the Read Request Size that it can handle. For i.MX6 family it's fixed at 512 bytes by default. If a memory read larger than the limit is requested, the CPU responds with Completer Abort (CA) (on i.MX6 Unsupported Request (UR) is returned instead due to a design error). The i.MX6 documentation states that the limit can be changed by writing to the PCIE_PL_MRCCR0 register, however there is a fixed (and undocumented) maximum (CX_REMOTE_RD_REQ_SIZE constant). Tests indicate that values larger than 512 bytes don't work, though. This patch makes the RTL8111 work on i.MX6. Signed-off-by: Krzysztof Hałasa <khalasa@piap.pl> --- While ATM needed only on ARM, this version is compiled in on all archs.