Message ID | ghbnqkeh9k.fsf@quad.gouders.net |
---|---|
State | Not Applicable |
Headers | show |
On Fri, Sep 12, 2014 at 10:05 PM, Dirk Gouders <dirk@gouders.net> wrote: > Dirk Gouders <dirk@gouders.net> writes: > >> Dirk Gouders <dirk@gouders.net> writes: >> >>> Bjorn Helgaas <bhelgaas@google.com> writes: >>> >>>> On Thu, Sep 11, 2014 at 3:24 PM, Dirk Gouders <dirk@gouders.net> wrote: >>>>> Bjorn Helgaas <bhelgaas@google.com> writes: >>>>> >>>>>> On Thu, Sep 11, 2014 at 2:33 PM, Dirk Gouders <dirk@gouders.net> wrote: >>>>>>> What I was currently trying was to construct a test-environment so that >>>>>>> I do not need to do tests and diagnosis on a busy machine. >>>>>>> >>>>>>> I noticed that this problem seems to start with the narrow Root >>>>>>> Bridge window (00-07) but every other machine that I had a look at, >>>>>>> starts with (00-ff), so those will not trigger my problem. >>>>>>> >>>>>>> I thought I could perhaps try to shrink the window in >>>>>>> acpi_pci_root_add() to trigger the problem and that kind of works: it >>>>>>> triggers it but not exactly the same way, because it basically ends at >>>>>>> this code in pci_scan_bridge(): >>>>>>> >>>>>>> if (max >= bus->busn_res.end) { >>>>>>> dev_warn(&dev->dev, "can't allocate child bus %02x from %pR (pass %d)\n", >>>>>>> max, &bus->busn_res, pass); >>>>>>> goto out; >>>>>>> } >>>>>>> >>>>>>> If this could work but I am just missing a small detail, I would be >>>>>>> glad to hear about it and do the first tests this way. If it is >>>>>>> complete nonsense, I will just use the machine that triggers the problem >>>>>>> for the tests. >>>>>> >>>>>> I was about to suggest the same thing. If the problem is related to >>>>>> the bus number change, we should be able to force that to happen on a >>>>>> different machine. Your approach sounds good, so I'm guessing we just >>>>>> need a tweak. >>>>>> >>>>>> I would first double-check that the PCI adapters are identical, >>>>>> including the firmware on the card. Can you also include your patch >>>>>> and the resulting dmesg (with debug enabled as before)? >>>>> >>>>> Currently I am at home doing just tests for understanding and that I can >>>>> hopefully use when I am back in the office. >>>>> >>>>> I already noticed the the backup FC Adapter on the test machine is not >>>>> exactly the same: it is Rev. 1 whereas the one on the failing machine is >>>>> Rev. 2. >>>>> >>>>> So, here at home my tests let a NIC disappear. Different from the >>>>> original problem but I was just trying to reconstruct the szenario of a >>>>> misconfigured bridge causing a reconfiguration. >>>>> >>>>> What I was trying is: >>>>> >>>>> diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c >>>>> index e6ae603..fd146b3 100644 >>>>> --- a/drivers/acpi/pci_root.c >>>>> +++ b/drivers/acpi/pci_root.c >>>>> @@ -556,6 +556,7 @@ static int acpi_pci_root_add(struct acpi_device *device, >>>>> strcpy(acpi_device_name(device), ACPI_PCI_ROOT_DEVICE_NAME); >>>>> strcpy(acpi_device_class(device), ACPI_PCI_ROOT_CLASS); >>>>> device->driver_data = root; >>>>> + root->secondary.end = 0x02; >>>>> >>>>> pr_info(PREFIX "%s [%s] (domain %04x %pR)\n", >>>>> acpi_device_name(device), acpi_device_bid(device), >>>>> >>>>> The device that disappears is a NIC: >>>>> >>>>> 00:00.0 Host bridge: Intel Corporation Xeon E3-1200 v2/3rd Gen Core processor DRAM Controller (rev 09) >>>>> 00:02.0 VGA compatible controller: Intel Corporation Xeon E3-1200 v2/3rd Gen Core processor Graphics Controller (rev 09) >>>>> 00:14.0 USB controller: Intel Corporation 7 Series/C210 Series Chipset Family USB xHCI Host Controller (rev 04) >>>>> 00:16.0 Communication controller: Intel Corporation 7 Series/C210 Series Chipset Family MEI Controller #1 (rev 04) >>>>> 00:1a.0 USB controller: Intel Corporation 7 Series/C210 Series Chipset Family USB Enhanced Host Controller #2 (rev 04) >>>>> 00:1b.0 Audio device: Intel Corporation 7 Series/C210 Series Chipset Family High Definition Audio Controller (rev 04) >>>>> 00:1c.0 PCI bridge: Intel Corporation 7 Series/C210 Series Chipset Family PCI Express Root Port 1 (rev c4) >>>>> 00:1c.4 PCI bridge: Intel Corporation 7 Series/C210 Series Chipset Family PCI Express Root Port 5 (rev c4) >>>>> 00:1c.5 PCI bridge: Intel Corporation 7 Series/C210 Series Chipset Family PCI Express Root Port 6 (rev c4) >>>>> 00:1d.0 USB controller: Intel Corporation 7 Series/C210 Series Chipset Family USB Enhanced Host Controller #1 (rev 04) >>>>> 00:1e.0 PCI bridge: Intel Corporation 82801 PCI Bridge (rev a4) >>>>> 00:1f.0 ISA bridge: Intel Corporation B75 Express Chipset LPC Controller (rev 04) >>>>> 00:1f.2 SATA controller: Intel Corporation 7 Series/C210 Series Chipset Family 6-port SATA Controller [AHCI mode] (rev 04) >>>>> 00:1f.3 SMBus: Intel Corporation 7 Series/C210 Series Chipset Family SMBus Controller (rev 04) >>>>> 02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 06) >>>>> >>>>> This is the one that is missing with the above change: >>>>> 03:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 06) >>>> >>>> This situation is a little different, so I don't think you're >>>> reproducing the situation we want to test. On this box, you have: >>>> >>>> pci_bus 0000:00: root bus resource [bus 00-02] >>>> pci 0000:00:1c.0: PCI bridge to [bus 01] >>>> pci 0000:00:1c.4: PCI bridge to [bus 02] >>>> >>>> so we find all the devices on bus 00 and bus 02 (there's nothing on >>>> bus 01). My guess is the 03:00.0 device is normally behind the >>>> 00:1c.5 bridge, but we don't even scan behind that bridge because we >>>> can't allocate a secondary bus number for it (we're not smart enough >>>> to take advantage of the empty bus 01). >>>> >>>> On the failing box, it's different because we *do* have unused bus >>>> number space, and we do actually reconfigure the bridge to use it. >>>> It's just that the FC adapter doesn't respond when we use the new bus >>>> number for it. >>>> >>>> You might be able to do something similar on the test box by: >>>> >>>> - Keeping your root->secondary.end = 02 patch, so you still have [bus 00-02]. >>>> - Ignoring bridges 00:1c.0 and 00:1c.4. I would just test for those >>>> devfns in pci_scan_device() and when you see them, return NULL instead >>>> of trying to read the vendor ID. >>>> >>>> Then 00:1c.5 is probably configured by the BIOS for [bus 03], but >>>> that's outside the root bridge range, so we should reconfigure it to >>>> use [bus 01]. Then we should scan behind it, and we'll probably >>>> discover the NIC that was previously at 03:00.0. The device *should* >>>> just work at the new bus number, since it probably doesn't have the >>>> same bug the FC adapter does. >>> >>> Thanks for the explanation. I tried to ignore the two bridges but the >>> machine stopped with the "reconfiguring" message. >>> >>> Anyway, if I understood you correctly with the backup FC adapter I have >>> good chances, because there is the needed unused bus number space and I >>> don't have to ignore bridges. I will test in a few hours and report. >> >> It turned out that there is no unused bus number space on the test >> machine: >> >> -[0000:00]-+-01.0-[01-02]--+-0d.0-[02]-- >> | +-0e.0 Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) >> | \-0e.1 Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) >> +-02.0 Broadcom BCM5785 [HT1000] Legacy South Bridge >> +-02.1 Broadcom BCM5785 [HT1000] IDE >> +-02.2 Broadcom BCM5785 [HT1000] LPC >> +-03.0 Broadcom BCM5785 [HT1000] USB >> +-03.1 Broadcom BCM5785 [HT1000] USB >> +-03.2 Broadcom BCM5785 [HT1000] USB >> +-06.0-[03]-- >> +-07.0-[04]--+-04.0 Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet >> | \-04.1 Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet >> +-08.0-[05]-- >> +-09.0-[06]-- >> +-0a.0-[07]----00.0 LSI Logic / Symbios Logic FC949ES Fibre Channel Adapter >> +-0b.0-[08]-- >> +-0c.0 Advanced Micro Devices, Inc. [AMD/ATI] ES1000 >> +-18.0 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration >> +-18.1 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Address Map >> +-18.2 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] DRAM Controller >> +-18.3 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Miscellaneous Control >> +-19.0 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration >> +-19.1 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Address Map >> +-19.2 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] DRAM Controller >> \-19.3 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Miscellaneous Control >> >> So, I used the following changes to create the space and limit the root >> bridge window: >> >> diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c >> index e6ae603..a41066b 100644 >> --- a/drivers/acpi/pci_root.c >> +++ b/drivers/acpi/pci_root.c >> @@ -556,6 +556,7 @@ static int acpi_pci_root_add(struct acpi_device *device, >> strcpy(acpi_device_name(device), ACPI_PCI_ROOT_DEVICE_NAME); >> strcpy(acpi_device_class(device), ACPI_PCI_ROOT_CLASS); >> device->driver_data = root; >> + root->secondary.end = 0x06; >> >> pr_info(PREFIX "%s [%s] (domain %04x %pR)\n", >> acpi_device_name(device), acpi_device_bid(device), >> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c >> index e3cf8a2..d8dc02d 100644 >> --- a/drivers/pci/probe.c >> +++ b/drivers/pci/probe.c >> @@ -1323,6 +1323,9 @@ static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) >> struct pci_dev *dev; >> u32 l; >> >> + if (devfn == PCI_DEVFN(0x08, 0) || devfn == PCI_DEVFN(0x09,0)) >> + return NULL; >> + >> if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) >> return NULL; >> >> And to me it looks as if that is the situation, I need for testing >> Yinghai's patches; the FC Adapter disappeared similar to that on the >> other machine (find the dmesg output at the end): >> >> -[0000:00]-+-01.0-[01-02]--+-0d.0-[02]-- >> | +-0e.0 Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) >> | \-0e.1 Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) >> +-02.0 Broadcom BCM5785 [HT1000] Legacy South Bridge >> +-02.1 Broadcom BCM5785 [HT1000] IDE >> +-02.2 Broadcom BCM5785 [HT1000] LPC >> +-03.0 Broadcom BCM5785 [HT1000] USB >> +-03.1 Broadcom BCM5785 [HT1000] USB >> +-03.2 Broadcom BCM5785 [HT1000] USB >> +-06.0-[03]-- >> +-07.0-[04]--+-04.0 Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet >> | \-04.1 Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet >> +-0a.0-[05]-- >> +-0b.0-[06]-- >> +-0c.0 Advanced Micro Devices, Inc. [AMD/ATI] ES1000 >> +-18.0 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration >> +-18.1 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Address Map >> +-18.2 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] DRAM Controller >> +-18.3 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Miscellaneous Control >> +-19.0 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration >> +-19.1 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Address Map >> +-19.2 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] DRAM Controller >> \-19.3 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Miscellaneous Control >> >> >> So, I wanted to test the patches but unfortunately, the patches do not >> apply cleanly; git am refuses to take the files (unknown format) and git >> apply gives errors. I tried to apply them against Linus' current, v3.16, >> v3.15 and v3.14. What am I probably doing wrong, Yinghai? > > Yinghai, > > I now applied your patches and tested them: > > echo 1 > /sys/bus/pci/devices/0000\:00\:0a.0/pcie_link_disable > echo 0 > /sys/bus/pci/devices/0000\:00\:0a.0/pcie_link_disable You'll probably need to trigger a rescan: echo 1 > /sys/bus/pci/rescan > The FC Adapter did not show up, this is the dmesg output (I also tested > with 0b.0): > > [ 143.294168] pcieport 0000:00:0a.0: pcie_link_disable_set: lnk_ctrl = 18 > [ 148.284456] pcieport 0000:00:0a.0: pcie_link_disable_set: lnk_ctrl = 8 > [ 304.065942] pcieport 0000:00:0b.0: pcie_link_disable_set: lnk_ctrl = 18 > [ 309.035278] pcieport 0000:00:0b.0: pcie_link_disable_set: lnk_ctrl = 8 > > So, probably my test environment does not work as expected and I have to > test it on the failing machine. > > I hope I applied the patches correctly, I attach them to this mail. > > Dirk > > > From b57b339bf10237e234c491c58f6dd0a1f575c34e Mon Sep 17 00:00:00 2001 > From: Dirk Gouders <dirk@gouders.net> > Date: Fri, 12 Sep 2014 21:16:06 +0200 > Subject: [PATCH 1/4] PCI: Add generic pcie_link_disable > > Remove not needed return value checking that Linus pointed out before. > > Will use it from /sys/.../pcie/link_disable > > Signed-off-by: Yinghai Lu <yinghai@kernel.org> > --- > drivers/pci/Makefile | 2 +- > drivers/pci/pcie-link.c | 42 ++++++++++++++++++++++++++++++++++++++++++ > include/linux/pci.h | 2 ++ > 3 files changed, 45 insertions(+), 1 deletion(-) > create mode 100644 drivers/pci/pcie-link.c > > diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile > index e04fe2d..eab9feb 100644 > --- a/drivers/pci/Makefile > +++ b/drivers/pci/Makefile > @@ -4,7 +4,7 @@ > > obj-y += access.o bus.o probe.o host-bridge.o remove.o pci.o \ > pci-driver.o search.o pci-sysfs.o rom.o setup-res.o \ > - irq.o vpd.o setup-bus.o vc.o > + irq.o vpd.o setup-bus.o pcie-link.o vc.o > obj-$(CONFIG_PROC_FS) += proc.o > obj-$(CONFIG_SYSFS) += slot.o > > diff --git a/drivers/pci/pcie-link.c b/drivers/pci/pcie-link.c > new file mode 100644 > index 0000000..e10d0ba > --- /dev/null > +++ b/drivers/pci/pcie-link.c > @@ -0,0 +1,42 @@ > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/pci.h> > +#include <linux/errno.h> > +#include <linux/jiffies.h> > +#include <linux/delay.h> > + > +int pcie_link_disable_get(struct pci_dev *dev) > +{ > + u16 lnk_ctrl; > + if (!pci_is_pcie(dev)) > + return 0; > + > + pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &lnk_ctrl); > + > + return !!(lnk_ctrl & PCI_EXP_LNKCTL_LD); > +} > + > +void pcie_link_disable_set(struct pci_dev *dev, int bit) > +{ > + u16 lnk_ctrl, old_lnk_ctrl; > + > + if (!pci_is_pcie(dev)) > + return; > + > + pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &lnk_ctrl); > + old_lnk_ctrl = lnk_ctrl; > + > + if (!bit) > + lnk_ctrl &= ~PCI_EXP_LNKCTL_LD; > + else > + lnk_ctrl |= PCI_EXP_LNKCTL_LD; > + > + if (old_lnk_ctrl == lnk_ctrl) > + return; > + > + pcie_capability_write_word(dev, PCI_EXP_LNKCTL, lnk_ctrl); > + > + dev_printk(KERN_DEBUG, &dev->dev, "%s: lnk_ctrl = %x\n", __func__, > + lnk_ctrl); > +} > +EXPORT_SYMBOL(pcie_link_disable_set); > diff --git a/include/linux/pci.h b/include/linux/pci.h > index 61978a4..926fcb4 100644 > --- a/include/linux/pci.h > +++ b/include/linux/pci.h > @@ -778,6 +778,8 @@ struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, > struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, > int busnr); > void pcie_update_link_speed(struct pci_bus *bus, u16 link_status); > +void pcie_link_disable_set(struct pci_dev *dev, int bit); > +int pcie_link_disable_get(struct pci_dev *dev); > struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr, > const char *name, > struct hotplug_slot *hotplug); > -- > 2.1.0 > > > From 4435354e0d99e409d0140256d8162c0046139843 Mon Sep 17 00:00:00 2001 > From: Dirk Gouders <dirk@gouders.net> > Date: Fri, 12 Sep 2014 21:25:18 +0200 > Subject: [PATCH 3/4] PCI, sysfs: Add pcie attrs for pcie device under pci dev > dir. > > Will put link_disable and link_retrain > > Signed-off-by: Yinghai Lu <yinghai@kernel.org> > --- > drivers/pci/Makefile | 2 +- > drivers/pci/pci-sysfs.c | 1 + > drivers/pci/pci.h | 1 + > drivers/pci/pcie-sysfs.c | 23 +++++++++++++++++++++++ > 4 files changed, 26 insertions(+), 1 deletion(-) > create mode 100644 drivers/pci/pcie-sysfs.c > > diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile > index eab9feb..43523dd 100644 > --- a/drivers/pci/Makefile > +++ b/drivers/pci/Makefile > @@ -4,7 +4,7 @@ > > obj-y += access.o bus.o probe.o host-bridge.o remove.o pci.o \ > pci-driver.o search.o pci-sysfs.o rom.o setup-res.o \ > - irq.o vpd.o setup-bus.o pcie-link.o vc.o > + irq.o vpd.o setup-bus.o pcie-link.o pcie-sysfs.o vc.o > obj-$(CONFIG_PROC_FS) += proc.o > obj-$(CONFIG_SYSFS) += slot.o > > diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c > index 9ff0a90..6f20e5d 100644 > --- a/drivers/pci/pci-sysfs.c > +++ b/drivers/pci/pci-sysfs.c > @@ -1566,6 +1566,7 @@ static struct attribute_group pci_dev_attr_group = { > > static const struct attribute_group *pci_dev_attr_groups[] = { > &pci_dev_attr_group, > + &pci_dev_pcie_attr_group, > &pci_dev_hp_attr_group, > #ifdef CONFIG_PCI_IOV > &sriov_dev_attr_group, > diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h > index 0601890..cc2977c 100644 > --- a/drivers/pci/pci.h > +++ b/drivers/pci/pci.h > @@ -152,6 +152,7 @@ static inline int pci_no_d1d2(struct pci_dev *dev) > extern const struct attribute_group *pci_dev_groups[]; > extern const struct attribute_group *pcibus_groups[]; > extern struct device_type pci_dev_type; > +extern struct attribute_group pci_dev_pcie_attr_group; > extern const struct attribute_group *pci_bus_groups[]; > > > diff --git a/drivers/pci/pcie-sysfs.c b/drivers/pci/pcie-sysfs.c > new file mode 100644 > index 0000000..b65e065 > --- /dev/null > +++ b/drivers/pci/pcie-sysfs.c > @@ -0,0 +1,23 @@ > +#include <linux/kernel.h> > +#include <linux/pci.h> > + > +static struct attribute *pci_dev_pcie_dev_attrs[] = { > + NULL, > +}; > + > +static umode_t pci_dev_pcie_attrs_are_visible(struct kobject *kobj, > + struct attribute *a, int n) > +{ > + struct device *dev = container_of(kobj, struct device, kobj); > + struct pci_dev *pdev = to_pci_dev(dev); > + > + if (!pci_is_pcie(pdev)) > + return 0; > + > + return a->mode; > +} > + > +struct attribute_group pci_dev_pcie_attr_group = { > + .is_visible = pci_dev_pcie_attrs_are_visible, > + .attrs = pci_dev_pcie_dev_attrs, > +}; > -- > 2.1.0 > > > From 8cd5b6a3b380b730893cf67e7d611fe256baeaed Mon Sep 17 00:00:00 2001 > From: Dirk Gouders <dirk@gouders.net> > Date: Fri, 12 Sep 2014 21:31:53 +0200 > Subject: [PATCH 4/4] PCI: Add link_disable in /sysfs for pcie device > > Found PCIe cards from one vendor, will not respond to scan from bridge, > if we change bus number setting in bridge device. > > Have to do link disable/enable on the pcie root port. > > So try to expose link disable bit of pcie link control register. We can use > echo 1 > /sys/..../link_disable > echo 0 > /sys/..../link_disable > to bring the pcie device back to respond to scan. > > Signed-off-by: Yinghai Lu <yinghai@kernel.org> > --- > drivers/pci/pcie-sysfs.c | 33 +++++++++++++++++++++++++++++++++ > 1 file changed, 33 insertions(+) > > diff --git a/drivers/pci/pcie-sysfs.c b/drivers/pci/pcie-sysfs.c > index b65e065..d4f6d4f 100644 > --- a/drivers/pci/pcie-sysfs.c > +++ b/drivers/pci/pcie-sysfs.c > @@ -1,7 +1,35 @@ > #include <linux/kernel.h> > #include <linux/pci.h> > > +static ssize_t > +pcie_link_disable_show(struct device *dev, struct device_attribute *attr, > + char *buf) > +{ > + struct pci_dev *pdev = to_pci_dev(dev); > + > + return sprintf(buf, "%u\n", pcie_link_disable_get(pdev)); > +} > +static ssize_t > +pcie_link_disable_store(struct device *dev, struct device_attribute *attr, > + const char *buf, size_t count) > +{ > + struct pci_dev *pdev = to_pci_dev(dev); > + unsigned long val; > + > + if (kstrtoul(buf, 0, &val) < 0) > + return -EINVAL; > + > + pcie_link_disable_set(pdev, val); > + > + return count; > +} > + > +static struct device_attribute pcie_link_disable_attr = > + __ATTR(pcie_link_disable, 0644, > + pcie_link_disable_show, pcie_link_disable_store); > + > static struct attribute *pci_dev_pcie_dev_attrs[] = { > + &pcie_link_disable_attr.attr, > NULL, > }; > > @@ -14,6 +42,11 @@ static umode_t pci_dev_pcie_attrs_are_visible(struct kobject *kobj, > if (!pci_is_pcie(pdev)) > return 0; > > + if (a == &pcie_link_disable_attr.attr) > + if ((pci_pcie_type(pdev) != PCI_EXP_TYPE_ROOT_PORT) && > + (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM)) > + return 0; > + > return a->mode; > } > > -- > 2.1.0 > > -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Fri, Sep 12, 2014 at 2:05 PM, Dirk Gouders <dirk@gouders.net> wrote: > ... > Yinghai, > > I now applied your patches and tested them: > > echo 1 > /sys/bus/pci/devices/0000\:00\:0a.0/pcie_link_disable > echo 0 > /sys/bus/pci/devices/0000\:00\:0a.0/pcie_link_disable > > The FC Adapter did not show up, this is the dmesg output (I also tested > with 0b.0): > > [ 143.294168] pcieport 0000:00:0a.0: pcie_link_disable_set: lnk_ctrl = 18 > [ 148.284456] pcieport 0000:00:0a.0: pcie_link_disable_set: lnk_ctrl = 8 > [ 304.065942] pcieport 0000:00:0b.0: pcie_link_disable_set: lnk_ctrl = 18 > [ 309.035278] pcieport 0000:00:0b.0: pcie_link_disable_set: lnk_ctrl = 8 > > So, probably my test environment does not work as expected and I have to > test it on the failing machine. I think you probably did reproduce the problem, it's just that it wasn't fixed by bouncing the link. What if you try the following: DEV=00:0a.0 setpci -s$DEV BRIDGE_CONTROL.W=0x0040 sleep 1 setpci -s$DEV BRIDGE_CONTROL.W=0x0000 sleep 1 echo 1 > /sys/bus/pci/rescan Thanks to your patch, we reconfigured the secondary bus number of bridge 00:0a.0. The commands above should reset the FC device behind that bridge. I suspect it will then respond when we rescan that bus. Bjorn -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Fri, Sep 12, 2014 at 1:05 PM, Dirk Gouders <dirk@gouders.net> wrote: > Dirk Gouders <dirk@gouders.net> writes: > > I now applied your patches and tested them: > > echo 1 > /sys/bus/pci/devices/0000\:00\:0a.0/pcie_link_disable > echo 0 > /sys/bus/pci/devices/0000\:00\:0a.0/pcie_link_disable > > The FC Adapter did not show up, this is the dmesg output (I also tested > with 0b.0): > > [ 143.294168] pcieport 0000:00:0a.0: pcie_link_disable_set: lnk_ctrl = 18 > [ 148.284456] pcieport 0000:00:0a.0: pcie_link_disable_set: lnk_ctrl = 8 > [ 304.065942] pcieport 0000:00:0b.0: pcie_link_disable_set: lnk_ctrl = 18 > [ 309.035278] pcieport 0000:00:0b.0: pcie_link_disable_set: lnk_ctrl = 8 > > So, probably my test environment does not work as expected and I have to > test it on the failing machine. You need to rescan the pci devices. like echo 1 > /sys/bus/pci/rescan Thanks Yinghai -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Yinghai Lu <yinghai@kernel.org> writes: > On Fri, Sep 12, 2014 at 1:05 PM, Dirk Gouders <dirk@gouders.net> wrote: >> Dirk Gouders <dirk@gouders.net> writes: >> >> I now applied your patches and tested them: >> >> echo 1 > /sys/bus/pci/devices/0000\:00\:0a.0/pcie_link_disable >> echo 0 > /sys/bus/pci/devices/0000\:00\:0a.0/pcie_link_disable >> >> The FC Adapter did not show up, this is the dmesg output (I also tested >> with 0b.0): >> >> [ 143.294168] pcieport 0000:00:0a.0: pcie_link_disable_set: lnk_ctrl = 18 >> [ 148.284456] pcieport 0000:00:0a.0: pcie_link_disable_set: lnk_ctrl = 8 >> [ 304.065942] pcieport 0000:00:0b.0: pcie_link_disable_set: lnk_ctrl = 18 >> [ 309.035278] pcieport 0000:00:0b.0: pcie_link_disable_set: lnk_ctrl = 8 >> >> So, probably my test environment does not work as expected and I have to >> test it on the failing machine. > > You need to rescan the pci devices. > like > > echo 1 > /sys/bus/pci/rescan Thank you (all) for your suggestions. I tried both: the plain rescan and Bjorn's suggestion but the FC adapter seems to be very shy: [ 143.294168] pcieport 0000:00:0a.0: pcie_link_disable_set: lnk_ctrl = 18 [ 148.284456] pcieport 0000:00:0a.0: pcie_link_disable_set: lnk_ctrl = 8 [ 304.065942] pcieport 0000:00:0b.0: pcie_link_disable_set: lnk_ctrl = 18 [ 309.035278] pcieport 0000:00:0b.0: pcie_link_disable_set: lnk_ctrl = 8 [ 2514.440442] pcieport 0000:00:0a.0: pcie_link_disable_set: lnk_ctrl = 18 [ 2554.819381] pcieport 0000:00:0a.0: pcie_link_disable_set: lnk_ctrl = 8 [ 3339.722154] pci_scan_child_bus: pci_bus 0000:00: scanning bus [ 3339.722215] pci_scan_bridge: pci 0000:00:01.0: scanning [bus 01-02] behind bridge, pass 0 [ 3339.722222] pci_scan_child_bus: pci_bus 0000:01: scanning bus [ 3339.722251] pci_scan_bridge: pci 0000:01:0d.0: scanning [bus 02-02] behind bridge, pass 0 [ 3339.722256] pci_scan_child_bus: pci_bus 0000:02: scanning bus [ 3339.722287] pci_scan_child_bus: pci_bus 0000:02: bus scan returning with max=02 [ 3339.722292] pci_scan_bridge: pci 0000:01:0d.0: scanning [bus 02-02] behind bridge, pass 1 [ 3339.722297] pci_scan_child_bus: pci_bus 0000:01: bus scan returning with max=02 [ 3339.722302] pci_scan_bridge: pci 0000:00:06.0: scanning [bus 03-03] behind bridge, pass 0 [ 3339.722307] pci_scan_child_bus: pci_bus 0000:03: scanning bus [ 3339.722332] pci_scan_child_bus: pci_bus 0000:03: bus scan returning with max=03 [ 3339.722337] pci_scan_bridge: pci 0000:00:07.0: scanning [bus 04-04] behind bridge, pass 0 [ 3339.722341] pci_scan_child_bus: pci_bus 0000:04: scanning bus [ 3339.722364] pci_scan_child_bus: pci_bus 0000:04: bus scan returning with max=04 [ 3339.722369] pci_scan_bridge: pcieport 0000:00:0a.0: scanning [bus 05-05] behind bridge, pass 0 [ 3339.722373] pci_scan_child_bus: pci_bus 0000:05: scanning bus [ 3339.722377] pci_scan_child_bus: pci_bus 0000:05: bus scan returning with max=05 [ 3339.722381] pci_scan_bridge: pcieport 0000:00:0b.0: scanning [bus 06-06] behind bridge, pass 0 [ 3339.722386] pci_scan_child_bus: pci_bus 0000:06: scanning bus [ 3339.722389] pci_scan_child_bus: pci_bus 0000:06: bus scan returning with max=06 [ 3339.722394] pci_scan_bridge: pci 0000:00:01.0: scanning [bus 01-02] behind bridge, pass 1 [ 3339.722400] pci_scan_bridge: pci 0000:00:06.0: scanning [bus 03-03] behind bridge, pass 1 [ 3339.722404] pci_scan_bridge: pci 0000:00:07.0: scanning [bus 04-04] behind bridge, pass 1 [ 3339.722409] pci_scan_bridge: pcieport 0000:00:0a.0: scanning [bus 05-05] behind bridge, pass 1 [ 3339.722414] pci_scan_bridge: pcieport 0000:00:0b.0: scanning [bus 06-06] behind bridge, pass 1 [ 3339.722418] pci_scan_child_bus: pci_bus 0000:00: bus scan returning with max=06 [ 3339.722455] pci 0000:01:0d.0: PCI bridge to [bus 02] [ 3339.722466] pci 0000:00:06.0: PCI bridge to [bus 03] [ 3583.321906] pci_scan_child_bus: pci_bus 0000:00: scanning bus [ 3583.321974] pci_scan_bridge: pci 0000:00:01.0: scanning [bus 01-02] behind bridge, pass 0 [ 3583.321982] pci_scan_child_bus: pci_bus 0000:01: scanning bus [ 3583.322032] pci_scan_bridge: pci 0000:01:0d.0: scanning [bus 02-02] behind bridge, pass 0 [ 3583.322037] pci_scan_child_bus: pci_bus 0000:02: scanning bus [ 3583.322070] pci_scan_child_bus: pci_bus 0000:02: bus scan returning with max=02 [ 3583.322076] pci_scan_bridge: pci 0000:01:0d.0: scanning [bus 02-02] behind bridge, pass 1 [ 3583.322081] pci_scan_child_bus: pci_bus 0000:01: bus scan returning with max=02 [ 3583.322087] pci_scan_bridge: pci 0000:00:06.0: scanning [bus 03-03] behind bridge, pass 0 [ 3583.322092] pci_scan_child_bus: pci_bus 0000:03: scanning bus [ 3583.322121] pci_scan_child_bus: pci_bus 0000:03: bus scan returning with max=03 [ 3583.322126] pci_scan_bridge: pci 0000:00:07.0: scanning [bus 04-04] behind bridge, pass 0 [ 3583.322130] pci_scan_child_bus: pci_bus 0000:04: scanning bus [ 3583.322155] pci_scan_child_bus: pci_bus 0000:04: bus scan returning with max=04 [ 3583.322160] pci_scan_bridge: pcieport 0000:00:0a.0: scanning [bus 05-05] behind bridge, pass 0 [ 3583.322164] pci_scan_child_bus: pci_bus 0000:05: scanning bus [ 3583.322168] pci_scan_child_bus: pci_bus 0000:05: bus scan returning with max=05 [ 3583.322177] pci_scan_bridge: pcieport 0000:00:0b.0: scanning [bus 06-06] behind bridge, pass 0 [ 3583.322182] pci_scan_child_bus: pci_bus 0000:06: scanning bus [ 3583.322185] pci_scan_child_bus: pci_bus 0000:06: bus scan returning with max=06 [ 3583.322191] pci_scan_bridge: pci 0000:00:01.0: scanning [bus 01-02] behind bridge, pass 1 [ 3583.322196] pci_scan_bridge: pci 0000:00:06.0: scanning [bus 03-03] behind bridge, pass 1 [ 3583.322202] pci_scan_bridge: pci 0000:00:07.0: scanning [bus 04-04] behind bridge, pass 1 [ 3583.322207] pci_scan_bridge: pcieport 0000:00:0a.0: scanning [bus 05-05] behind bridge, pass 1 [ 3583.322212] pci_scan_bridge: pcieport 0000:00:0b.0: scanning [bus 06-06] behind bridge, pass 1 [ 3583.322216] pci_scan_child_bus: pci_bus 0000:00: bus scan returning with max=06 [ 3583.322262] pci 0000:01:0d.0: PCI bridge to [bus 02] [ 3583.322273] pci 0000:00:06.0: PCI bridge to [bus 03] # lspci -tv -[0000:00]-+-01.0-[01-02]--+-0d.0-[02]-- | +-0e.0 Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) | \-0e.1 Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) +-02.0 Broadcom BCM5785 [HT1000] Legacy South Bridge +-02.1 Broadcom BCM5785 [HT1000] IDE +-02.2 Broadcom BCM5785 [HT1000] LPC +-03.0 Broadcom BCM5785 [HT1000] USB +-03.1 Broadcom BCM5785 [HT1000] USB +-03.2 Broadcom BCM5785 [HT1000] USB +-06.0-[03]-- +-07.0-[04]--+-04.0 Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet | \-04.1 Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet +-0a.0-[05]-- +-0b.0-[06]-- +-0c.0 Advanced Micro Devices, Inc. [AMD/ATI] ES1000 +-18.0 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration +-18.1 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Address Map +-18.2 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] DRAM Controller +-18.3 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Miscellaneous Control +-19.0 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration +-19.1 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Address Map +-19.2 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] DRAM Controller \-19.3 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Miscellaneous Control -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Fri, Sep 12, 2014 at 1:54 PM, Dirk Gouders <dirk@gouders.net> wrote: > Yinghai Lu <yinghai@kernel.org> writes: > >> On Fri, Sep 12, 2014 at 1:05 PM, Dirk Gouders <dirk@gouders.net> wrote: >>> Dirk Gouders <dirk@gouders.net> writes: > -[0000:00]-+-01.0-[01-02]--+-0d.0-[02]-- > | +-0e.0 Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) > | \-0e.1 Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) > +-02.0 Broadcom BCM5785 [HT1000] Legacy South Bridge > +-02.1 Broadcom BCM5785 [HT1000] IDE > +-02.2 Broadcom BCM5785 [HT1000] LPC > +-03.0 Broadcom BCM5785 [HT1000] USB > +-03.1 Broadcom BCM5785 [HT1000] USB > +-03.2 Broadcom BCM5785 [HT1000] USB > +-06.0-[03]-- > +-07.0-[04]--+-04.0 Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet > | \-04.1 Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet > +-0a.0-[05]-- > +-0b.0-[06]-- what is "lspci -tv" and "lspci -vvxxx" look like before your patch that cut down end bus to 07 ...? Thanks Yinghai -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Yinghai Lu <yinghai@kernel.org> writes: > On Fri, Sep 12, 2014 at 1:54 PM, Dirk Gouders <dirk@gouders.net> wrote: >> Yinghai Lu <yinghai@kernel.org> writes: >> >>> On Fri, Sep 12, 2014 at 1:05 PM, Dirk Gouders <dirk@gouders.net> wrote: >>>> Dirk Gouders <dirk@gouders.net> writes: >> -[0000:00]-+-01.0-[01-02]--+-0d.0-[02]-- >> | +-0e.0 Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) >> | \-0e.1 Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) >> +-02.0 Broadcom BCM5785 [HT1000] Legacy South Bridge >> +-02.1 Broadcom BCM5785 [HT1000] IDE >> +-02.2 Broadcom BCM5785 [HT1000] LPC >> +-03.0 Broadcom BCM5785 [HT1000] USB >> +-03.1 Broadcom BCM5785 [HT1000] USB >> +-03.2 Broadcom BCM5785 [HT1000] USB >> +-06.0-[03]-- >> +-07.0-[04]--+-04.0 Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet >> | \-04.1 Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet >> +-0a.0-[05]-- >> +-0b.0-[06]-- > > what is "lspci -tv" and "lspci -vvxxx" look like before your patch that cut down > end bus to 07 ...? Rebooted with 3.16 kernel: # lspci -tv -[0000:00]-+-01.0-[01-02]--+-0d.0-[02]-- | +-0e.0 Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) | \-0e.1 Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) +-02.0 Broadcom BCM5785 [HT1000] Legacy South Bridge +-02.1 Broadcom BCM5785 [HT1000] IDE +-02.2 Broadcom BCM5785 [HT1000] LPC +-03.0 Broadcom BCM5785 [HT1000] USB +-03.1 Broadcom BCM5785 [HT1000] USB +-03.2 Broadcom BCM5785 [HT1000] USB +-06.0-[03]-- +-07.0-[04]--+-04.0 Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet | \-04.1 Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet +-08.0-[05]-- +-09.0-[06]-- +-0a.0-[07]----00.0 LSI Logic / Symbios Logic FC949ES Fibre Channel Adapter +-0b.0-[08]-- +-0c.0 Advanced Micro Devices, Inc. [AMD/ATI] ES1000 +-18.0 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration +-18.1 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Address Map +-18.2 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] DRAM Controller +-18.3 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Miscellaneous Control +-19.0 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration +-19.1 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Address Map +-19.2 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] DRAM Controller \-19.3 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Miscellaneous Control # lspci -vvxxx 00:01.0 PCI bridge: Broadcom BCM5785 [HT1000] PCI/PCI-X Bridge (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort+ <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 Bus: primary=00, secondary=01, subordinate=02, sec-latency=64 I/O behind bridge: 00007000-00008fff Memory behind bridge: ff100000-ff1fffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [90] PCI-X bridge device Secondary Status: 64bit+ 133MHz+ SCD- USC- SCO- SRD- Freq=133MHz Status: Dev=00:01.0 64bit- 133MHz- SCD- USC- SCO- SRD- Upstream: Capacity=0 CommitmentLimit=0 Downstream: Capacity=0 CommitmentLimit=0 Capabilities: [a0] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [b0] HyperTransport: Slave or Primary Interface Command: BaseUnitID=1 UnitCnt=3 MastHost- DefDir- Link Control 0: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config 0: MLWI=8bit MLWO=8bit LWI=8bit LWO=8bit Link Control 1: CFlE- CST- CFE- <LkFail- Init- EOC+ TXO+ <CRCErr=0 Link Config 1: MLWI=8bit MLWO=8bit LWI=N/C LWO=N/C Revision ID: 0.00 Capabilities: [d8] Subsystem: Device 0000:0000 00: 66 11 36 00 07 00 10 08 00 00 04 06 00 40 01 00 10: 00 00 00 00 00 00 00 00 00 01 02 40 71 81 00 24 20: 10 ff 10 ff f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 90 00 00 00 00 00 00 00 60 00 04 00 40: 00 00 00 00 00 00 00 01 01 00 00 20 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 c0 74 00 c0 60: c5 60 30 18 00 00 00 00 00 00 00 01 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 01 04 08 00 01 08 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 07 a0 c3 00 08 00 00 00 00 00 00 00 00 00 00 00 a0: 08 b0 01 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 b0: 08 d8 61 00 20 00 00 00 c0 00 00 77 00 05 75 00 c0: 02 00 35 00 00 00 00 00 00 00 00 00 0c 05 03 03 d0: 00 00 00 00 e0 0f 04 00 0d 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 80 00 40 00 04 00 00 00 00 00 00 00 00 00 00:02.0 Host bridge: Broadcom BCM5785 [HT1000] Legacy South Bridge Subsystem: Broadcom Device 0201 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 00: 66 11 05 02 07 01 00 02 00 00 00 06 00 40 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 66 11 01 02 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: a0 28 12 04 00 ff 00 00 07 00 00 00 10 04 10 04 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 8f c1 f3 1d 00 00 00 40 36 01 00 01 70: 0b 00 00 00 00 00 00 00 80 00 00 00 00 00 00 00 80: 80 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 90: 81 05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:02.1 IDE interface: Broadcom BCM5785 [HT1000] IDE (prog-if 8a [Master SecP PriP]) Subsystem: Broadcom BCM5785 [HT1000] IDE Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Region 0: I/O ports at 01f0 [size=8] Region 1: I/O ports at 03f4 Region 2: I/O ports at 0170 [size=8] Region 3: I/O ports at 0374 Region 4: I/O ports at ffa0 [size=16] Kernel driver in use: pata_serverworks 00: 66 11 14 02 05 00 00 02 00 8a 01 01 10 40 80 00 10: f1 01 00 00 f5 03 00 00 71 01 00 00 75 03 00 00 20: a1 ff 00 00 00 00 00 00 00 00 00 00 66 11 14 02 30: 00 00 00 00 b0 00 00 00 00 00 00 00 00 00 00 00 40: 5d 5d 5d 5d ff ff ff ff f0 f1 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 0f 04 03 00 00 00 00 00 60: 00 00 00 00 01 07 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 01 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:02.2 ISA bridge: Broadcom BCM5785 [HT1000] LPC Subsystem: Broadcom Device 0230 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 00: 66 11 34 02 07 01 00 02 00 00 01 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 66 11 30 02 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 0c 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: ff ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 11 90: 40 00 06 ff 00 ff 00 00 00 00 00 00 7c 64 00 00 a0: 00 00 00 00 03 03 02 ff 00 0a 00 0a ff ff 0f 00 b0: 03 a9 00 04 09 00 00 00 20 00 80 00 80 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:03.0 USB controller: Broadcom BCM5785 [HT1000] USB (rev 01) (prog-if 10 [OHCI]) Subsystem: Broadcom BCM5785 [HT1000] USB Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 10 Region 0: Memory at ff6e8000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at d400 [size=256] Capabilities: [dc] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Bridge: PM- B3+ Kernel driver in use: ohci-pci 00: 66 11 23 02 17 01 b0 02 01 10 03 0c 10 40 80 00 10: 00 80 6e ff 01 d4 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 66 11 23 02 30: 00 00 00 00 dc 00 00 00 00 00 00 00 0a 01 00 00 40: 80 ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 02 00 e0: 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:03.1 USB controller: Broadcom BCM5785 [HT1000] USB (rev 01) (prog-if 10 [OHCI]) Subsystem: Broadcom BCM5785 [HT1000] USB Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 10 Region 0: Memory at ff6e9000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at d800 [size=256] Capabilities: [dc] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Bridge: PM- B3+ Kernel driver in use: ohci-pci 00: 66 11 23 02 17 01 b0 02 01 10 03 0c 10 40 00 00 10: 00 90 6e ff 01 d8 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 66 11 23 02 30: 00 00 00 00 dc 00 00 00 00 00 00 00 0a 01 00 00 40: 80 ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 02 00 e0: 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:03.2 USB controller: Broadcom BCM5785 [HT1000] USB (rev 01) (prog-if 20 [EHCI]) Subsystem: Broadcom BCM5785 [HT1000] USB Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 10 Region 0: Memory at ff6ea000 (32-bit, non-prefetchable) [size=4K] Region 1: I/O ports at e800 [size=256] Capabilities: [dc] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0+,D1+,D2+,D3hot+,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Bridge: PM- B3+ Kernel driver in use: ehci-pci 00: 66 11 23 02 17 01 b0 02 01 20 03 0c 10 40 00 00 10: 00 a0 6e ff 01 e8 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 66 11 23 02 30: 00 00 00 00 dc 00 00 00 00 00 00 00 0a 01 00 00 40: 80 ff 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 20 20 00 00 00 20 00 00 00 20 00 00 00 20 00 00 70: 00 20 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 01 00 00 00 00 00 08 c0 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 01 00 02 7e e0: 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:06.0 PCI bridge: Broadcom BCM5780 [HT2000] PCI-X bridge (rev a3) (prog-if 00 [Normal decode]) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 Bus: primary=00, secondary=03, subordinate=03, sec-latency=64 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr+ DiscTmrStat- DiscTmrSERREn- Capabilities: [90] PCI-X bridge device Secondary Status: 64bit+ 133MHz+ SCD- USC- SCO- SRD- Freq=133MHz Status: Dev=00:06.0 64bit- 133MHz- SCD- USC- SCO- SRD- Upstream: Capacity=0 CommitmentLimit=0 Downstream: Capacity=0 CommitmentLimit=0 Capabilities: [a0] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [b0] HyperTransport: Slave or Primary Interface Command: BaseUnitID=6 UnitCnt=6 MastHost- DefDir- Link Control 0: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config 0: MLWI=16bit MLWO=16bit LWI=16bit LWO=16bit Link Control 1: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 Link Config 1: MLWI=8bit MLWO=8bit LWI=8bit LWO=8bit Revision ID: 0.00 00: 66 11 30 01 06 00 10 00 a3 00 04 06 00 40 01 00 10: 00 00 00 00 00 00 00 00 00 03 03 40 f1 01 00 22 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 90 00 00 00 00 00 00 00 60 00 04 02 40: 00 00 00 00 00 00 00 00 00 00 00 20 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 ca 53 00 c0 60: 05 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 70: 00 00 00 00 20 03 00 00 00 01 04 08 00 00 08 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 07 a0 c3 00 30 00 00 00 00 00 00 00 00 00 00 00 a0: 08 b0 01 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 b0: 08 00 c6 00 20 00 11 11 20 00 00 00 00 06 75 00 c0: 02 05 35 00 00 00 00 00 00 00 00 00 0c 56 03 03 d0: 00 00 00 00 e0 0f 04 00 00 00 00 00 00 00 00 00 e0: 00 00 00 07 00 00 00 00 00 ff ca 20 00 00 00 00 f0: 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00:07.0 PCI bridge: Broadcom BCM5780 [HT2000] PCI-X bridge (rev a3) (prog-if 00 [Normal decode]) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 Bus: primary=00, secondary=04, subordinate=04, sec-latency=64 Memory behind bridge: ff200000-ff2fffff Prefetchable memory behind bridge: 00000000cfd00000-00000000cfdfffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=slow >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [90] PCI-X bridge device Secondary Status: 64bit+ 133MHz+ SCD- USC- SCO- SRD- Freq=133MHz Status: Dev=00:07.0 64bit- 133MHz- SCD- USC- SCO- SRD- Upstream: Capacity=0 CommitmentLimit=0 Downstream: Capacity=0 CommitmentLimit=0 Capabilities: [a0] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 00: 66 11 30 01 06 00 10 00 a3 00 04 06 00 40 01 00 10: 00 00 00 00 00 00 00 00 00 04 04 40 f1 01 00 24 20: 20 ff 20 ff d1 cf d1 cf 00 00 00 00 00 00 00 00 30: 00 00 00 00 90 00 00 00 00 00 00 00 60 00 04 00 40: 00 00 00 00 00 00 00 00 00 00 00 20 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 c8 00 00 c0 60: 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 70: 00 00 00 00 20 01 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 07 a0 c3 00 38 00 00 00 00 00 00 00 00 00 00 00 a0: 08 00 01 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 b0: 08 00 c0 00 00 00 11 00 00 00 00 00 00 00 75 00 c0: 02 00 35 00 00 00 00 00 00 00 00 00 0c 00 03 03 d0: 00 00 00 00 e0 0f 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 ff 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:08.0 PCI bridge: Broadcom BCM5780 [HT2000] PCI-Express Bridge (rev a3) (prog-if 00 [Normal decode]) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Bus: primary=00, secondary=05, subordinate=05, sec-latency=64 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [a0] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [b0] Express (v1) Root Port (Slot-), MSI 00 DevCap: MaxPayload 512 bytes, PhantFunc 0 ExtTag- RBE- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #1, Speed 2.5GT/s, Width x8, ASPM L0s L1, Exit Latency L0s <4us, L1 <16us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Kernel driver in use: pcieport 00: 66 11 32 01 06 00 10 00 a3 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 05 05 40 f1 01 00 02 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 60 00 04 00 40: 00 00 00 00 01 00 00 00 00 00 00 20 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0 60: 01 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 70: 00 00 09 8f 84 34 00 00 00 00 01 00 00 00 00 00 80: 01 00 00 00 20 10 70 2b 72 0a 18 00 01 00 00 fb 90: 90 03 80 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 08 b0 01 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 b0: 10 00 41 00 82 09 00 00 00 00 00 00 81 6c 02 01 c0: 08 00 81 00 00 00 08 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:09.0 PCI bridge: Broadcom BCM5780 [HT2000] PCI-Express Bridge (rev a3) (prog-if 00 [Normal decode]) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Bus: primary=00, secondary=06, subordinate=06, sec-latency=64 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [a0] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [b0] Express (v1) Root Port (Slot-), MSI 00 DevCap: MaxPayload 512 bytes, PhantFunc 0 ExtTag- RBE- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #2, Speed 2.5GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <4us, L1 <16us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Kernel driver in use: pcieport 00: 66 11 32 01 06 00 10 00 a3 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 06 06 40 f1 01 00 02 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 60 00 04 00 40: 00 00 00 00 01 00 00 00 00 00 00 20 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0 60: 01 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 70: 00 00 09 8f 84 34 00 00 00 00 01 00 00 00 00 00 80: 01 00 00 00 20 10 70 2b 72 0a 18 00 01 00 00 fb 90: 90 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 08 b0 01 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 b0: 10 00 41 00 82 09 00 00 00 00 00 00 41 6c 02 02 c0: 08 00 01 00 00 00 10 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0a.0 PCI bridge: Broadcom BCM5780 [HT2000] PCI-Express Bridge (rev a3) (prog-if 00 [Normal decode]) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Bus: primary=00, secondary=07, subordinate=07, sec-latency=64 I/O behind bridge: 00009000-0000bfff Memory behind bridge: ff300000-ff5fffff Prefetchable memory behind bridge: 00000000cfe00000-00000000cfefffff Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [a0] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [b0] Express (v1) Root Port (Slot-), MSI 00 DevCap: MaxPayload 512 bytes, PhantFunc 0 ExtTag- RBE- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #3, Speed 2.5GT/s, Width x8, ASPM L0s L1, Exit Latency L0s <4us, L1 <16us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Kernel driver in use: pcieport 00: 66 11 32 01 07 00 10 00 a3 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 07 07 40 91 b1 00 22 20: 30 ff 50 ff e1 cf e1 cf 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 60 00 04 00 40: 00 00 00 00 01 00 00 00 00 00 0c 20 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0 60: 01 00 08 01 00 00 00 00 00 00 00 01 00 00 00 00 70: 24 00 09 0f 84 34 00 00 00 00 01 00 00 00 00 00 80: 01 00 00 00 20 10 70 2b 72 0a 18 00 02 60 00 fb 90: 90 03 80 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 08 b0 01 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 b0: 10 00 41 00 82 09 00 00 00 00 00 00 81 6c 02 03 c0: 08 00 81 00 00 00 18 00 00 00 48 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0b.0 PCI bridge: Broadcom BCM5780 [HT2000] PCI-Express Bridge (rev a3) (prog-if 00 [Normal decode]) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 0 Bus: primary=00, secondary=08, subordinate=08, sec-latency=64 Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn- Capabilities: [a0] HyperTransport: MSI Mapping Enable+ Fixed- Mapping Address Base: 00000000fee00000 Capabilities: [b0] Express (v1) Root Port (Slot-), MSI 00 DevCap: MaxPayload 512 bytes, PhantFunc 0 ExtTag- RBE- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop- MaxPayload 128 bytes, MaxReadReq 128 bytes DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend- LnkCap: Port #4, Speed 2.5GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <4us, L1 <16us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 128 bytes Disabled- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x0, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible- RootCap: CRSVisible- RootSta: PME ReqID 0000, PMEStatus- PMEPending- Kernel driver in use: pcieport 00: 66 11 32 01 06 00 10 00 a3 00 04 06 00 00 01 00 10: 00 00 00 00 00 00 00 00 00 08 08 40 f1 01 00 02 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 a0 00 00 00 00 00 00 00 60 00 04 00 40: 00 00 00 00 01 00 00 00 00 00 00 20 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0 60: 01 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 70: 00 00 09 87 84 34 00 00 00 00 01 00 00 00 00 00 80: 01 00 00 00 20 10 70 2b 72 0a 18 00 01 00 00 fb 90: 90 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 08 b0 01 a8 00 00 e0 fe 00 00 00 00 00 00 00 00 b0: 10 00 41 00 82 09 00 00 00 00 00 00 41 6c 02 04 c0: 08 00 01 00 00 00 20 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:0c.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] ES1000 (rev 02) (prog-if 00 [VGA controller]) Subsystem: Advanced Micro Devices, Inc. [AMD/ATI] ES1000 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping+ SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 (2000ns min), Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 11 Region 0: Memory at d8000000 (32-bit, prefetchable) [size=128M] Region 1: I/O ports at e000 [size=256] Region 2: Memory at ff6f0000 (32-bit, non-prefetchable) [size=64K] Expansion ROM at ff6c0000 [disabled] [size=128K] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- 00: 02 10 5e 51 87 01 90 02 02 00 00 03 10 40 00 00 10: 08 00 00 d8 01 e0 00 00 00 00 6f ff 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 02 10 5e 51 30: 00 00 6c ff 50 00 00 00 00 00 00 00 0b 01 08 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 02 10 5e 51 50: 01 00 02 06 00 00 00 00 02 50 20 00 00 02 00 2f 60: 00 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.0 Host bridge: Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Revision ID: 1.02 Link Frequency: 1.0GHz Link Error: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC- LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- ExtRS- UCnfE- Capabilities: [a0] HyperTransport: Host or Secondary Interface Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Revision ID: 1.02 Link Frequency: 1.0GHz Link Error: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC- LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- ExtRS- UCnfE- Capabilities: [c0] HyperTransport: Host or Secondary Interface Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- Link Control: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=N/C DwFcInEn- LWO=N/C DwFcOutEn- Revision ID: 1.02 Link Frequency: 200MHz Link Error: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC- LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- ExtRS- UCnfE- 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 01 01 05 00 04 04 01 00 01 01 01 00 01 01 01 00 50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 60: 10 00 01 00 e4 00 00 00 00 c9 0e 0f 3c 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 a0 01 21 20 00 11 11 22 06 75 80 02 00 00 00 90: 56 04 51 02 00 00 ff 00 07 00 00 00 00 00 00 00 a0: 08 c0 01 21 20 00 11 11 22 06 75 80 02 00 00 00 b0: 13 56 13 04 00 00 00 00 03 00 00 00 00 00 00 00 c0: 08 00 01 21 d0 00 11 77 22 00 75 80 02 00 00 00 d0: 52 14 51 02 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.1 Host bridge: Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Address Map Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 03 00 00 00 00 00 7f 00 03 00 00 01 01 00 ff 01 50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00 60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00 70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 03 0a 00 00 00 0b 00 00 03 00 80 00 00 70 ff 00 c0: 13 10 00 00 00 f0 ff 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 03 00 00 ff 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.2 Host bridge: Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] DRAM Controller Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 01 00 00 00 01 10 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 ee e0 07 00 ee e0 07 80: 00 50 00 00 00 00 00 00 35 33 72 13 20 0a 10 00 90: 00 8c 8a 08 08 0b 5b 3e 00 00 00 00 06 08 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: e3 41 8f d6 36 00 00 00 fc d7 3d 36 00 ee 01 de c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: fa 00 92 2d 40 c7 04 78 7b 37 8b 14 98 22 01 12 e0: 78 00 49 b1 40 77 80 12 ba 05 c7 08 1c b0 00 08 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:18.3 Host bridge: Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Miscellaneous Control Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: ff 3b 00 00 40 00 50 00 00 00 00 00 00 00 00 00 50: f8 ff ff 7f 00 00 00 00 00 00 00 00 c0 d6 5d 3a 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 11 01 12 51 11 80 10 50 00 38 00 08 1b 22 00 00 80: 00 00 07 23 13 21 13 00 00 00 00 00 00 00 00 00 90: 02 00 00 00 64 00 00 00 f0 03 a0 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 3e 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 07 07 e2 04 10 27 00 20 00 25 00 00 e0: 00 00 00 00 20 09 64 00 1b 01 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:19.0 Host bridge: Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Capabilities: [80] HyperTransport: Host or Secondary Interface Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- Link Control: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=N/C DwFcInEn- LWO=N/C DwFcOutEn- Revision ID: 1.02 Link Frequency: 200MHz Link Error: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC- LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- ExtRS- UCnfE- Capabilities: [a0] HyperTransport: Host or Secondary Interface Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- Link Control: CFlE- CST- CFE- <LkFail- Init+ EOC- TXO- <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=16bit DwFcInEn- LWO=16bit DwFcOutEn- Revision ID: 1.02 Link Frequency: 1.0GHz Link Error: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC- LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- ExtRS- UCnfE- Capabilities: [c0] HyperTransport: Host or Secondary Interface Command: WarmRst+ DblEnd- DevNum=0 ChainSide- HostHide+ Slave- <EOCErr- DUL- Link Control: CFlE- CST- CFE- <LkFail+ Init- EOC+ TXO+ <CRCErr=0 IsocEn- LSEn- ExtCTL- 64b- Link Config: MLWI=16bit DwFcIn- MLWO=16bit DwFcOut- LWI=N/C DwFcInEn- LWO=N/C DwFcOutEn- Revision ID: 1.02 Link Frequency: 200MHz Link Error: <Prot- <Ovfl- <EOC- CTLTm- Link Frequency Capability: 200MHz+ 300MHz- 400MHz+ 500MHz- 600MHz+ 800MHz+ 1.0GHz+ 1.2GHz- 1.4GHz- 1.6GHz- Vend- Feature Capability: IsocFC- LDTSTOP+ CRCTM- ECTLT- 64bA- UIDRD- ExtRS- UCnfE- 00: 22 10 00 11 00 00 10 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 40: 04 04 01 00 01 01 05 00 01 01 01 00 01 01 01 00 50: 01 01 01 00 01 01 01 00 01 01 01 00 01 01 01 00 60: 11 00 01 00 e4 00 00 00 00 c9 0e 0f 14 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 08 a0 01 21 d0 00 11 77 22 00 75 80 02 00 00 00 90: 30 1c 00 04 00 00 00 00 00 00 00 00 00 00 00 00 a0: 08 c0 01 21 20 00 11 11 22 06 75 80 02 00 00 00 b0: 13 56 13 04 00 00 00 00 03 00 00 00 00 00 00 00 c0: 08 00 01 21 d0 00 11 77 22 00 75 80 02 00 00 00 d0: 00 76 34 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:19.1 Host bridge: Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Address Map Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 01 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 03 00 00 00 00 00 7f 00 03 00 00 01 01 00 ff 01 50: 00 00 00 00 02 00 00 00 00 00 00 00 03 00 00 00 60: 00 00 00 00 04 00 00 00 00 00 00 00 05 00 00 00 70: 00 00 00 00 06 00 00 00 00 00 00 00 07 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 03 0a 00 00 00 0b 00 00 03 00 80 00 00 70 ff 00 c0: 13 10 00 00 00 f0 ff 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 03 00 00 ff 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:19.2 Host bridge: Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] DRAM Controller Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 02 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 01 00 00 00 01 20 00 00 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 de e0 0f 00 de e0 0f 80: 00 50 00 00 00 00 00 00 35 33 72 13 20 0a 10 00 90: 00 8c 83 08 08 0b 5b 3e 00 00 00 00 06 08 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: ac 7a 2c d5 36 00 00 00 fb d0 03 38 01 9c 80 08 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 01 00 00 66 00 06 0b 81 30 00 c0 42 0c 06 00 14 e0: 91 60 00 a4 00 c2 01 00 32 20 60 85 4c 02 01 82 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00:19.3 Host bridge: Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Miscellaneous Control Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- 00: 22 10 03 11 00 00 00 00 00 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: ff 3b 00 00 40 00 50 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 90 61 00 60: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 11 01 12 51 11 80 10 50 00 38 00 08 1b 22 00 00 80: 00 00 07 23 13 21 13 00 00 00 00 00 00 00 00 00 90: 02 00 00 00 64 00 00 00 30 00 aa 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 3f 00 00 20 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 07 07 e2 04 10 27 00 20 00 25 00 00 e0: 00 00 00 00 20 08 61 00 1b 01 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:0d.0 PCI bridge: Broadcom BCM5785 [HT1000] PCI/PCI-X Bridge (rev c0) (prog-if 00 [Normal decode]) Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64, Cache Line Size: 64 bytes Bus: primary=01, secondary=02, subordinate=02, sec-latency=64 Secondary status: 66MHz+ FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort+ <SERR- <PERR- BridgeCtl: Parity- SERR- NoISA+ VGA- MAbort- >Reset- FastB2B- PriDiscTmr- SecDiscTmr+ DiscTmrStat- DiscTmrSERREn- Capabilities: [90] PCI-X bridge device Secondary Status: 64bit+ 133MHz+ SCD- USC- SCO- SRD- Freq=conv Status: Dev=01:0d.0 64bit+ 133MHz+ SCD- USC- SCO- SRD- Upstream: Capacity=8 CommitmentLimit=8 Downstream: Capacity=8 CommitmentLimit=8 Capabilities: [88] Subsystem: Device cf33:2db6 00: 66 11 04 01 16 00 30 02 c0 00 04 06 10 40 01 00 10: 00 00 00 00 00 00 00 00 01 02 02 40 f1 01 20 22 20: f0 ff 00 00 f1 ff 01 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 90 00 00 00 00 00 00 00 00 00 04 02 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 c0 13 00 c0 60: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 04 00 00 00 00 00 00 0d 00 00 00 33 cf b6 2d 90: 07 88 03 00 68 01 03 00 08 00 08 00 08 00 08 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:0e.0 IDE interface: Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) (prog-if 8f [Master SecP SecO PriP PriO]) Subsystem: Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 Interrupt: pin A routed to IRQ 11 Region 0: I/O ports at 8080 [size=8] Region 1: I/O ports at 8000 [size=4] Region 2: I/O ports at 7c00 [size=8] Region 3: I/O ports at 7880 [size=4] Region 4: I/O ports at 7800 [size=16] Region 5: Memory at ff1fe000 (32-bit, non-prefetchable) [size=8K] Expansion ROM at ff1c0000 [disabled] [size=128K] Capabilities: [60] PCI-X non-bridge device Command: DPERE- ERO- RBC=512 OST=8 Status: Dev=01:0e.0 64bit+ 133MHz+ SCD- USC- DC=simple DMMRBC=512 DMOST=8 DMCRS=32 RSCEM- 266MHz- 533MHz- Capabilities: [90] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 Kernel driver in use: sata_svw 00: 66 11 4b 02 07 01 10 02 00 8f 01 01 00 40 80 00 10: 81 80 00 00 01 80 00 00 01 7c 00 00 81 78 00 00 20: 01 78 00 00 00 e0 1f ff 00 00 00 00 66 11 4b 02 30: 00 00 1c ff 60 00 00 00 00 00 00 00 0b 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 07 90 40 00 70 01 03 0a 00 00 00 00 00 00 00 00 70: 28 00 00 00 00 00 00 00 84 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 01 a0 02 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01:0e.1 IDE interface: Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) (prog-if 8f [Master SecP SecO PriP PriO]) Subsystem: Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 Interrupt: pin A routed to IRQ 11 Region 0: I/O ports at 8c00 [size=8] Region 1: I/O ports at 8880 [size=4] Region 2: I/O ports at 8800 [size=8] Region 3: I/O ports at 8480 [size=4] Region 4: I/O ports at 8400 [size=16] Capabilities: [60] PCI-X non-bridge device Command: DPERE- ERO- RBC=512 OST=8 Status: Dev=01:0e.0 64bit+ 133MHz+ SCD- USC- DC=simple DMMRBC=512 DMOST=8 DMCRS=32 RSCEM- 266MHz- 533MHz- Capabilities: [90] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [a0] MSI: Enable- Count=1/1 Maskable- 64bit- Address: 00000000 Data: 0000 00: 66 11 4b 02 07 01 30 02 00 8f 01 01 00 40 80 00 10: 01 8c 00 00 81 88 00 00 01 88 00 00 81 84 00 00 20: 01 84 00 00 00 00 00 00 00 00 00 00 66 11 4b 02 30: 00 00 00 00 60 00 00 00 00 00 00 00 0b 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 60: 07 90 40 00 70 01 03 0a 00 00 00 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 01 a0 02 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 05 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04:04.0 Ethernet controller: Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet (rev 03) Subsystem: Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 (16000ns min), Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 64 Region 0: Memory at ff2d0000 (64-bit, non-prefetchable) [size=64K] Region 2: Memory at ff2c0000 (64-bit, non-prefetchable) [size=64K] Expansion ROM at <ignored> [disabled] Capabilities: [40] PCI-X non-bridge device Command: DPERE- ERO- RBC=512 OST=1 Status: Dev=04:04.0 64bit+ 133MHz+ SCD- USC- DC=simple DMMRBC=2048 DMOST=1 DMCRS=16 RSCEM- 266MHz- 533MHz- Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable+ DSel=0 DScale=1 PME- Capabilities: [50] Vital Product Data Product Name: Broadcom NetXtreme Gigabit Ethernet Controller Read-only fields: [PN] Part number: BCM95780 [EC] Engineering changes: 106679-15 [SN] Serial number: 0123456789 [MN] Manufacture ID: 31 34 65 34 [RV] Reserved: checksum bad, 28 byte(s) reserved Read/write fields: [YA] Asset tag: XYZ01234567 [RW] Read-write area: 107 byte(s) free End Capabilities: [58] MSI: Enable+ Count=1/8 Maskable- 64bit+ Address: 00000000fee0100c Data: 4161 Kernel driver in use: tg3 00: e4 14 6a 16 06 01 b0 02 03 00 00 02 10 40 80 00 10: 04 00 2d ff 00 00 00 00 04 00 2c ff 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 e4 14 6a 16 30: 00 00 94 01 40 00 00 00 00 00 00 00 05 01 40 00 40: 07 48 00 00 20 04 43 04 01 50 02 c0 00 21 00 64 50: 03 58 fc 80 00 00 00 78 05 00 87 00 0c 10 e0 fe 60: 00 00 00 00 61 41 00 00 98 02 03 80 00 40 14 76 70: ea 10 00 00 c7 00 00 80 00 00 00 00 00 00 00 00 80: e4 14 6a 16 0e 00 00 40 34 00 13 04 82 50 08 04 90: 09 ba 00 01 00 00 00 e6 00 00 00 00 76 00 00 00 a0: 00 00 00 00 ae 01 00 00 00 00 00 00 a2 01 00 00 b0: 00 00 00 00 00 00 00 97 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 04:04.1 Ethernet controller: Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet (rev 03) Subsystem: Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx- Latency: 64 (16000ns min), Cache Line Size: 64 bytes Interrupt: pin B routed to IRQ 27 Region 0: Memory at ff2f0000 (64-bit, non-prefetchable) [size=64K] Region 2: Memory at ff2e0000 (64-bit, non-prefetchable) [size=64K] Capabilities: [40] PCI-X non-bridge device Command: DPERE- ERO+ RBC=512 OST=1 Status: Dev=04:04.1 64bit+ 133MHz+ SCD- USC- DC=simple DMMRBC=2048 DMOST=1 DMCRS=16 RSCEM- 266MHz- 533MHz- Capabilities: [48] Power Management version 2 Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold+) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=1 PME- Capabilities: [50] Vital Product Data Product Name: Broadcom NetXtreme Gigabit Ethernet Controller Read-only fields: [PN] Part number: BCM95780 [EC] Engineering changes: 106679-15 [SN] Serial number: 0123456789 [MN] Manufacture ID: 31 34 65 34 [RV] Reserved: checksum bad, 28 byte(s) reserved Read/write fields: [YA] Asset tag: XYZ01234567 [RW] Read-write area: 107 byte(s) free End Capabilities: [58] MSI: Enable- Count=1/8 Maskable- 64bit+ Address: 180e811b201ebbc4 Data: 85c0 Kernel driver in use: tg3 00: e4 14 6a 16 06 01 b0 02 03 00 00 02 10 40 80 00 10: 04 00 2f ff 00 00 00 00 04 00 2e ff 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 e4 14 6a 16 30: 00 00 00 00 40 00 00 00 00 00 00 00 09 02 40 00 40: 07 48 02 00 21 04 43 04 01 50 02 c0 00 20 00 64 50: 03 58 fc 80 00 00 00 78 05 00 86 00 c4 bb 1e 20 60: 1b 81 0e 18 c0 85 00 00 9a 02 03 80 00 40 14 76 70: 8a 12 00 00 c7 00 00 00 00 00 00 00 00 00 00 00 80: e4 14 6a 16 d7 6b c5 3f 34 00 00 00 fe 50 08 04 90: 01 ba 00 09 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 04 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 07:00.0 Fibre Channel: LSI Logic / Symbios Logic FC949ES Fibre Channel Adapter (rev 01) Subsystem: LSI Logic / Symbios Logic Device 5010 Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR+ FastB2B- DisINTx- Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR+ <PERR- INTx- Latency: 0, Cache Line Size: 64 bytes Interrupt: pin A routed to IRQ 3 Region 0: I/O ports at b000 [size=256] Region 1: Memory at ff5fc000 (64-bit, non-prefetchable) [size=16K] Region 3: Memory at ff5e0000 (64-bit, non-prefetchable) [size=64K] Expansion ROM at ff400000 [disabled] [size=1M] Capabilities: [50] Power Management version 2 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-) Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME- Capabilities: [68] Express (v1) Endpoint, MSI 00 DevCap: MaxPayload 4096 bytes, PhantFunc 0, Latency L0s <64ns, L1 <1us ExtTag+ AttnBtn- AttnInd- PwrInd- RBE- FLReset- DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported- RlxdOrd+ ExtTag- PhantFunc- AuxPwr- NoSnoop+ MaxPayload 128 bytes, MaxReadReq 512 bytes DevSta: CorrErr- UncorrErr+ FatalErr- UnsuppReq+ AuxPwr- TransPend- LnkCap: Port #0, Speed 2.5GT/s, Width x8, ASPM L0s L1, Exit Latency L0s <64ns, L1 <1us ClockPM- Surprise- LLActRep- BwNot- LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk- ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt- LnkSta: Speed 2.5GT/s, Width x8, TrErr- Train- SlotClk- DLActive- BWMgmt- ABWMgmt- Capabilities: [98] MSI: Enable- Count=1/1 Maskable- 64bit+ Address: 0000000000000000 Data: 0000 Capabilities: [b0] MSI-X: Enable- Count=1 Masked- Vector table: BAR=1 offset=00002000 PBA: BAR=1 offset=00003000 00: 00 10 46 06 07 01 10 40 01 00 04 0c 10 00 00 00 10: 01 b0 00 00 04 c0 5f ff 00 00 00 00 04 00 5e ff 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 10 10 50 30: 00 00 40 ff 50 00 00 00 00 00 00 00 03 01 00 00 40: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50: 01 68 02 06 00 00 00 00 00 00 00 00 00 00 00 00 60: 00 00 00 00 00 07 00 00 10 98 01 00 25 00 00 00 70: 10 28 0a 00 81 0c 00 00 00 00 81 00 00 00 00 00 80: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 00 00 00 00 00 00 00 00 05 b0 80 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 11 00 00 00 01 20 00 00 01 30 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Fri, Sep 12, 2014 at 3:05 PM, Dirk Gouders <dirk@gouders.net> wrote: > Yinghai Lu <yinghai@kernel.org> writes: > >> On Fri, Sep 12, 2014 at 1:54 PM, Dirk Gouders <dirk@gouders.net> wrote: >>> Yinghai Lu <yinghai@kernel.org> writes: >>> >>>> On Fri, Sep 12, 2014 at 1:05 PM, Dirk Gouders <dirk@gouders.net> wrote: >>>>> Dirk Gouders <dirk@gouders.net> writes: >>> -[0000:00]-+-01.0-[01-02]--+-0d.0-[02]-- >>> | +-0e.0 Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) >>> | \-0e.1 Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) >>> +-02.0 Broadcom BCM5785 [HT1000] Legacy South Bridge >>> +-02.1 Broadcom BCM5785 [HT1000] IDE >>> +-02.2 Broadcom BCM5785 [HT1000] LPC >>> +-03.0 Broadcom BCM5785 [HT1000] USB >>> +-03.1 Broadcom BCM5785 [HT1000] USB >>> +-03.2 Broadcom BCM5785 [HT1000] USB >>> +-06.0-[03]-- >>> +-07.0-[04]--+-04.0 Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet >>> | \-04.1 Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet >>> +-0a.0-[05]-- >>> +-0b.0-[06]-- >> >> what is "lspci -tv" and "lspci -vvxxx" look like before your patch that cut down >> end bus to 07 ...? > > Rebooted with 3.16 kernel: > > # lspci -tv > > -[0000:00]-+-01.0-[01-02]--+-0d.0-[02]-- > | +-0e.0 Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) > | \-0e.1 Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) > +-02.0 Broadcom BCM5785 [HT1000] Legacy South Bridge > +-02.1 Broadcom BCM5785 [HT1000] IDE > +-02.2 Broadcom BCM5785 [HT1000] LPC > +-03.0 Broadcom BCM5785 [HT1000] USB > +-03.1 Broadcom BCM5785 [HT1000] USB > +-03.2 Broadcom BCM5785 [HT1000] USB > +-06.0-[03]-- > +-07.0-[04]--+-04.0 Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet > | \-04.1 Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet > +-08.0-[05]-- > +-09.0-[06]-- > +-0a.0-[07]----00.0 LSI Logic / Symbios Logic FC949ES Fibre Channel Adapter > +-0b.0-[08]-- where are 00:08.0 and 00:09.0 going? Did you just skip them in "cut end bus patch" ? Proper simulation could be: 1. remove 07:00.0 echo 1 > /sys/bus/pci/devices/0000:07:00.0/remove 2. change bus range in 00:0a.0 bus setpci -s 00:0a.0 0x1c.l=0x00101000 3. remove 00:0a.0 echo 1 > /sys/bus/pci/devices/0000:00:0a.0/remove 4. rescan pci echo 1 > /sys/bus/pci/rescan 5. reset pcie link from 00:0a.0 setpci -s 00:0a.0 0xc0.b=0x18 sleep 1s setpci -s 00:0a.0 0xc0.b=0x08 6. rescan pci bus echo 1 > /sys/bus/pci/rescan -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Yinghai Lu <yinghai@kernel.org> writes: > On Fri, Sep 12, 2014 at 3:05 PM, Dirk Gouders <dirk@gouders.net> wrote: >> Yinghai Lu <yinghai@kernel.org> writes: >> >>> On Fri, Sep 12, 2014 at 1:54 PM, Dirk Gouders <dirk@gouders.net> wrote: >>>> Yinghai Lu <yinghai@kernel.org> writes: >>>> >>>>> On Fri, Sep 12, 2014 at 1:05 PM, Dirk Gouders <dirk@gouders.net> wrote: >>>>>> Dirk Gouders <dirk@gouders.net> writes: >>>> -[0000:00]-+-01.0-[01-02]--+-0d.0-[02]-- >>>> | +-0e.0 Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) >>>> | \-0e.1 Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) >>>> +-02.0 Broadcom BCM5785 [HT1000] Legacy South Bridge >>>> +-02.1 Broadcom BCM5785 [HT1000] IDE >>>> +-02.2 Broadcom BCM5785 [HT1000] LPC >>>> +-03.0 Broadcom BCM5785 [HT1000] USB >>>> +-03.1 Broadcom BCM5785 [HT1000] USB >>>> +-03.2 Broadcom BCM5785 [HT1000] USB >>>> +-06.0-[03]-- >>>> +-07.0-[04]--+-04.0 Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet >>>> | \-04.1 Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet >>>> +-0a.0-[05]-- >>>> +-0b.0-[06]-- >>> >>> what is "lspci -tv" and "lspci -vvxxx" look like before your patch that cut down >>> end bus to 07 ...? >> >> Rebooted with 3.16 kernel: >> >> # lspci -tv >> >> -[0000:00]-+-01.0-[01-02]--+-0d.0-[02]-- >> | +-0e.0 Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) >> | \-0e.1 Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) >> +-02.0 Broadcom BCM5785 [HT1000] Legacy South Bridge >> +-02.1 Broadcom BCM5785 [HT1000] IDE >> +-02.2 Broadcom BCM5785 [HT1000] LPC >> +-03.0 Broadcom BCM5785 [HT1000] USB >> +-03.1 Broadcom BCM5785 [HT1000] USB >> +-03.2 Broadcom BCM5785 [HT1000] USB >> +-06.0-[03]-- >> +-07.0-[04]--+-04.0 Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet >> | \-04.1 Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet >> +-08.0-[05]-- >> +-09.0-[06]-- >> +-0a.0-[07]----00.0 LSI Logic / Symbios Logic FC949ES Fibre Channel Adapter >> +-0b.0-[08]-- > > where are 00:08.0 and 00:09.0 going? Did you just skip them in "cut > end bus patch" ? Yes, I skip them in pci_scan_device() to get the unused bus number space that 0a.0 and 0b.0 then can use when reconfiguration is triggered. > Proper simulation could be: > 1. remove 07:00.0 > echo 1 > /sys/bus/pci/devices/0000:07:00.0/remove > 2. change bus range in 00:0a.0 bus > setpci -s 00:0a.0 0x1c.l=0x00101000 > 3. remove 00:0a.0 > echo 1 > /sys/bus/pci/devices/0000:00:0a.0/remove > 4. rescan pci > echo 1 > /sys/bus/pci/rescan > 5. reset pcie link from 00:0a.0 > setpci -s 00:0a.0 0xc0.b=0x18 > sleep 1s > setpci -s 00:0a.0 0xc0.b=0x08 > 6. rescan pci bus > echo 1 > /sys/bus/pci/rescan OK, I did that (with 3.16) but the reconfiguration code doesn't get triggered. Here is what dmesg and lspci -tv say: [ 166.775570] pci_bus 0000:07: busn_res: [bus 07] is released [ 166.775744] pci_scan_child_bus: pci_bus 0000:00: scanning bus [ 166.775787] pci 0000:00:0a.0: [1166:0132] type 01 class 0x060400 [ 166.775902] pci 0000:00:0a.0: System wakeup disabled by ACPI [ 166.776031] pci_scan_bridge: pci 0000:00:01.0: scanning [bus 01-02] behind bridge, pass 0 [ 166.776038] pci_scan_child_bus: pci_bus 0000:01: scanning bus [ 166.776071] pci_scan_bridge: pci 0000:01:0d.0: scanning [bus 02-02] behind bridge, pass 0 [ 166.776076] pci_scan_child_bus: pci_bus 0000:02: scanning bus [ 166.776114] pci_scan_child_bus: pci_bus 0000:02: bus scan returning with max=02 [ 166.776119] pci_scan_bridge: pci 0000:01:0d.0: scanning [bus 02-02] behind bridge, pass 1 [ 166.776124] pci_scan_child_bus: pci_bus 0000:01: bus scan returning with max=02 [ 166.776130] pci_scan_bridge: pci 0000:00:06.0: scanning [bus 03-03] behind bridge, pass 0 [ 166.776134] pci_scan_child_bus: pci_bus 0000:03: scanning bus [ 166.776163] pci_scan_child_bus: pci_bus 0000:03: bus scan returning with max=03 [ 166.776168] pci_scan_bridge: pci 0000:00:07.0: scanning [bus 04-04] behind bridge, pass 0 [ 166.776172] pci_scan_child_bus: pci_bus 0000:04: scanning bus [ 166.776197] pci_scan_child_bus: pci_bus 0000:04: bus scan returning with max=04 [ 166.776202] pci_scan_bridge: pcieport 0000:00:08.0: scanning [bus 05-05] behind bridge, pass 0 [ 166.776206] pci_scan_child_bus: pci_bus 0000:05: scanning bus [ 166.776210] pci_scan_child_bus: pci_bus 0000:05: bus scan returning with max=05 [ 166.776215] pci_scan_bridge: pcieport 0000:00:09.0: scanning [bus 06-06] behind bridge, pass 0 [ 166.776219] pci_scan_child_bus: pci_bus 0000:06: scanning bus [ 166.776223] pci_scan_child_bus: pci_bus 0000:06: bus scan returning with max=06 [ 166.776227] pci_scan_bridge: pcieport 0000:00:0b.0: scanning [bus 08-08] behind bridge, pass 0 [ 166.776231] pci_scan_child_bus: pci_bus 0000:08: scanning bus [ 166.776235] pci_scan_child_bus: pci_bus 0000:08: bus scan returning with max=08 [ 166.776240] pci_scan_bridge: pci 0000:00:0a.0: scanning [bus 07-07] behind bridge, pass 0 [ 166.776284] pci_scan_child_bus: pci_bus 0000:07: scanning bus [ 166.776300] pci 0000:07:00.0: [1000:0646] type 00 class 0x0c0400 [ 166.776314] pci 0000:07:00.0: reg 0x10: [io 0xb000-0xb0ff] [ 166.776327] pci 0000:07:00.0: reg 0x14: [mem 0xff5fc000-0xff5fffff 64bit] [ 166.776340] pci 0000:07:00.0: reg 0x1c: [mem 0xff5e0000-0xff5effff 64bit] [ 166.776355] pci 0000:07:00.0: reg 0x30: [mem 0xff400000-0xff4fffff pref] [ 166.776396] pci 0000:07:00.0: supports D1 D2 [ 166.778033] pci_scan_child_bus: pci_bus 0000:07: fixups for bus [ 166.778038] pci 0000:00:0a.0: PCI bridge to [bus 07] [ 166.778045] pci 0000:00:0a.0: bridge window [io 0x0000-0x1fff] [ 166.778048] pci 0000:00:0a.0: bridge window [mem 0xff300000-0xff5fffff] [ 166.778054] pci 0000:00:0a.0: bridge window [mem 0xcfe00000-0xcfefffff 64bit pref] [ 166.778057] pci_scan_child_bus: pci_bus 0000:07: bus scan returning with max=07 [ 166.778062] pci_scan_bridge: pci 0000:00:01.0: scanning [bus 01-02] behind bridge, pass 1 [ 166.778068] pci_scan_bridge: pci 0000:00:06.0: scanning [bus 03-03] behind bridge, pass 1 [ 166.778073] pci_scan_bridge: pci 0000:00:07.0: scanning [bus 04-04] behind bridge, pass 1 [ 166.778079] pci_scan_bridge: pcieport 0000:00:08.0: scanning [bus 05-05] behind bridge, pass 1 [ 166.778084] pci_scan_bridge: pcieport 0000:00:09.0: scanning [bus 06-06] behind bridge, pass 1 [ 166.778089] pci_scan_bridge: pcieport 0000:00:0b.0: scanning [bus 08-08] behind bridge, pass 1 [ 166.778094] pci_scan_bridge: pci 0000:00:0a.0: scanning [bus 07-07] behind bridge, pass 1 [ 166.778098] pci_scan_child_bus: pci_bus 0000:00: bus scan returning with max=08 [ 166.778152] pci 0000:00:0a.0: BAR 8: assigned [mem 0x80000000-0x802fffff] [ 166.778159] pci 0000:00:0a.0: BAR 9: assigned [mem 0x200000000-0x2000fffff 64bit pref] [ 166.778164] pci 0000:00:0a.0: BAR 7: assigned [io 0x1000-0x2fff] [ 166.778169] pci 0000:01:0d.0: PCI bridge to [bus 02] [ 166.778179] pci 0000:00:06.0: PCI bridge to [bus 03] [ 166.778188] pci 0000:07:00.0: BAR 6: assigned [mem 0x80000000-0x800fffff pref] [ 166.778193] pci 0000:07:00.0: BAR 3: assigned [mem 0x80100000-0x8010ffff 64bit] [ 166.778204] pci 0000:07:00.0: BAR 1: assigned [mem 0x80110000-0x80113fff 64bit] [ 166.778213] pci 0000:07:00.0: BAR 0: assigned [io 0x1000-0x10ff] [ 166.778218] pci 0000:00:0a.0: PCI bridge to [bus 07] [ 166.778221] pci 0000:00:0a.0: bridge window [io 0x1000-0x2fff] [ 166.778226] pci 0000:00:0a.0: bridge window [mem 0x80000000-0x802fffff] [ 166.778229] pci 0000:00:0a.0: bridge window [mem 0x200000000-0x2000fffff 64bit pref] [ 166.778244] fixup_debug_start: pci 0000:00:0a.0: calling quirk_msi_ht_cap+0x0/0x50 [ 166.778251] pci 0000:00:0a.0: Found enabled HT MSI Mapping [ 167.800394] pci_scan_child_bus: pci_bus 0000:00: scanning bus [ 167.800456] pci_scan_bridge: pci 0000:00:01.0: scanning [bus 01-02] behind bridge, pass 0 [ 167.800463] pci_scan_child_bus: pci_bus 0000:01: scanning bus [ 167.800495] pci_scan_bridge: pci 0000:01:0d.0: scanning [bus 02-02] behind bridge, pass 0 [ 167.800501] pci_scan_child_bus: pci_bus 0000:02: scanning bus [ 167.800536] pci_scan_child_bus: pci_bus 0000:02: bus scan returning with max=02 [ 167.800541] pci_scan_bridge: pci 0000:01:0d.0: scanning [bus 02-02] behind bridge, pass 1 [ 167.800547] pci_scan_child_bus: pci_bus 0000:01: bus scan returning with max=02 [ 167.800552] pci_scan_bridge: pci 0000:00:06.0: scanning [bus 03-03] behind bridge, pass 0 [ 167.800556] pci_scan_child_bus: pci_bus 0000:03: scanning bus [ 167.800584] pci_scan_child_bus: pci_bus 0000:03: bus scan returning with max=03 [ 167.800589] pci_scan_bridge: pci 0000:00:07.0: scanning [bus 04-04] behind bridge, pass 0 [ 167.800593] pci_scan_child_bus: pci_bus 0000:04: scanning bus [ 167.800618] pci_scan_child_bus: pci_bus 0000:04: bus scan returning with max=04 [ 167.800623] pci_scan_bridge: pcieport 0000:00:08.0: scanning [bus 05-05] behind bridge, pass 0 [ 167.800627] pci_scan_child_bus: pci_bus 0000:05: scanning bus [ 167.800631] pci_scan_child_bus: pci_bus 0000:05: bus scan returning with max=05 [ 167.800635] pci_scan_bridge: pcieport 0000:00:09.0: scanning [bus 06-06] behind bridge, pass 0 [ 167.800640] pci_scan_child_bus: pci_bus 0000:06: scanning bus [ 167.800643] pci_scan_child_bus: pci_bus 0000:06: bus scan returning with max=06 [ 167.800648] pci_scan_bridge: pcieport 0000:00:0b.0: scanning [bus 08-08] behind bridge, pass 0 [ 167.800652] pci_scan_child_bus: pci_bus 0000:08: scanning bus [ 167.800656] pci_scan_child_bus: pci_bus 0000:08: bus scan returning with max=08 [ 167.800660] pci_scan_bridge: pcieport 0000:00:0a.0: scanning [bus 07-07] behind bridge, pass 0 [ 167.800664] pci_scan_child_bus: pci_bus 0000:07: scanning bus [ 167.800668] pci_scan_child_bus: pci_bus 0000:07: bus scan returning with max=07 [ 167.800673] pci_scan_bridge: pci 0000:00:01.0: scanning [bus 01-02] behind bridge, pass 1 [ 167.800678] pci_scan_bridge: pci 0000:00:06.0: scanning [bus 03-03] behind bridge, pass 1 [ 167.800683] pci_scan_bridge: pci 0000:00:07.0: scanning [bus 04-04] behind bridge, pass 1 [ 167.800689] pci_scan_bridge: pcieport 0000:00:08.0: scanning [bus 05-05] behind bridge, pass 1 [ 167.800693] pci_scan_bridge: pcieport 0000:00:09.0: scanning [bus 06-06] behind bridge, pass 1 [ 167.800698] pci_scan_bridge: pcieport 0000:00:0b.0: scanning [bus 08-08] behind bridge, pass 1 [ 167.800704] pci_scan_bridge: pcieport 0000:00:0a.0: scanning [bus 07-07] behind bridge, pass 1 [ 167.800708] pci_scan_child_bus: pci_bus 0000:00: bus scan returning with max=08 [ 167.800752] pci 0000:01:0d.0: PCI bridge to [bus 02] [ 167.800762] pci 0000:00:06.0: PCI bridge to [bus 03] # lspci -tv -[0000:00]-+-01.0-[01-02]--+-0d.0-[02]-- | +-0e.0 Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) | \-0e.1 Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) +-02.0 Broadcom BCM5785 [HT1000] Legacy South Bridge +-02.1 Broadcom BCM5785 [HT1000] IDE +-02.2 Broadcom BCM5785 [HT1000] LPC +-03.0 Broadcom BCM5785 [HT1000] USB +-03.1 Broadcom BCM5785 [HT1000] USB +-03.2 Broadcom BCM5785 [HT1000] USB +-06.0-[03]-- +-07.0-[04]--+-04.0 Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet | \-04.1 Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet +-08.0-[05]-- +-09.0-[06]-- +-0a.0-[07]----00.0 LSI Logic / Symbios Logic FC949ES Fibre Channel Adapter +-0b.0-[08]-- +-0c.0 Advanced Micro Devices, Inc. [AMD/ATI] ES1000 +-18.0 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration +-18.1 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Address Map +-18.2 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] DRAM Controller +-18.3 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Miscellaneous Control +-19.0 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration +-19.1 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Address Map +-19.2 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] DRAM Controller \-19.3 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Miscellaneous Control -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On Fri, Sep 12, 2014 at 5:11 PM, Dirk Gouders <dirk@gouders.net> wrote: > Yinghai Lu <yinghai@kernel.org> writes: > > Yes, I skip them in pci_scan_device() to get the unused bus number space > that 0a.0 and 0b.0 then can use when reconfiguration is triggered. That is not right. Can not let two bridges use same bus num. > >> Proper simulation could be: >> 1. remove 07:00.0 >> echo 1 > /sys/bus/pci/devices/0000:07:00.0/remove >> 2. change bus range in 00:0a.0 bus >> setpci -s 00:0a.0 0x1c.l=0x00101000 >> 3. remove 00:0a.0 >> echo 1 > /sys/bus/pci/devices/0000:00:0a.0/remove >> 4. rescan pci >> echo 1 > /sys/bus/pci/rescan >> 5. reset pcie link from 00:0a.0 >> setpci -s 00:0a.0 0xc0.b=0x18 >> sleep 1s >> setpci -s 00:0a.0 0xc0.b=0x08 >> 6. rescan pci bus >> echo 1 > /sys/bus/pci/rescan > > OK, I did that (with 3.16) but the reconfiguration code doesn't > get triggered. Here is what dmesg and lspci -tv say: 2 should be setpci -s 00:0a.0 0x18.l=0x00101000 -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
Yinghai Lu <yinghai@kernel.org> writes: > On Fri, Sep 12, 2014 at 5:11 PM, Dirk Gouders <dirk@gouders.net> wrote: >> Yinghai Lu <yinghai@kernel.org> writes: >> >> Yes, I skip them in pci_scan_device() to get the unused bus number space >> that 0a.0 and 0b.0 then can use when reconfiguration is triggered. > > That is not right. Can not let two bridges use same bus num. > >> >>> Proper simulation could be: >>> 1. remove 07:00.0 >>> echo 1 > /sys/bus/pci/devices/0000:07:00.0/remove >>> 2. change bus range in 00:0a.0 bus >>> setpci -s 00:0a.0 0x1c.l=0x00101000 >>> 3. remove 00:0a.0 >>> echo 1 > /sys/bus/pci/devices/0000:00:0a.0/remove >>> 4. rescan pci >>> echo 1 > /sys/bus/pci/rescan >>> 5. reset pcie link from 00:0a.0 >>> setpci -s 00:0a.0 0xc0.b=0x18 >>> sleep 1s >>> setpci -s 00:0a.0 0xc0.b=0x08 >>> 6. rescan pci bus >>> echo 1 > /sys/bus/pci/rescan >> >> OK, I did that (with 3.16) but the reconfiguration code doesn't >> get triggered. Here is what dmesg and lspci -tv say: > > 2 should be > setpci -s 00:0a.0 0x18.l=0x00101000 I'm very sorry for the late test result, Yinghai, I totally overlooked this correction. I'm not sure if it is still of interest but I now tried these corrected commands on the test machine with a vanilla 3.16 kernel. The FC adapter disappears but I cannot see the "bridge configuration invalid ..., reconfiguring" message, so I assume that the test situation is still not exactly matching that on the vx50 or am I missing something? lspci before and lspci + dmesg after above commands attached. Dirk - lspci before --------------------------------------------------------- -[0000:00]-+-01.0-[01-02]--+-0d.0-[02]-- | +-0e.0 Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) | \-0e.1 Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) +-02.0 Broadcom BCM5785 [HT1000] Legacy South Bridge +-02.1 Broadcom BCM5785 [HT1000] IDE +-02.2 Broadcom BCM5785 [HT1000] LPC +-03.0 Broadcom BCM5785 [HT1000] USB +-03.1 Broadcom BCM5785 [HT1000] USB +-03.2 Broadcom BCM5785 [HT1000] USB +-06.0-[03]-- +-07.0-[04]--+-04.0 Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet | \-04.1 Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet +-08.0-[05]-- +-09.0-[06]-- +-0a.0-[07]----00.0 LSI Logic / Symbios Logic FC949ES Fibre Channel Adapter +-0b.0-[08]-- +-0c.0 Advanced Micro Devices, Inc. [AMD/ATI] ES1000 +-18.0 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration +-18.1 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Address Map +-18.2 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] DRAM Controller +-18.3 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Miscellaneous Control +-19.0 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration +-19.1 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Address Map +-19.2 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] DRAM Controller \-19.3 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Miscellaneous Control - lspci after ---------------------------------------------------------- -[0000:00]-+-01.0-[01-02]--+-0d.0-[02]-- | +-0e.0 Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) | \-0e.1 Broadcom BCM5785 [HT1000] SATA (PATA/IDE Mode) +-02.0 Broadcom BCM5785 [HT1000] Legacy South Bridge +-02.1 Broadcom BCM5785 [HT1000] IDE +-02.2 Broadcom BCM5785 [HT1000] LPC +-03.0 Broadcom BCM5785 [HT1000] USB +-03.1 Broadcom BCM5785 [HT1000] USB +-03.2 Broadcom BCM5785 [HT1000] USB +-06.0-[03]-- +-07.0-[04]--+-04.0 Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet | \-04.1 Broadcom Corporation NetXtreme BCM5780 Gigabit Ethernet +-08.0-[05]-- +-09.0-[06]-- +-0a.0-[10]-- +-0b.0-[08]-- +-0c.0 Advanced Micro Devices, Inc. [AMD/ATI] ES1000 +-18.0 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration +-18.1 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Address Map +-18.2 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] DRAM Controller +-18.3 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Miscellaneous Control +-19.0 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] HyperTransport Technology Configuration +-19.1 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Address Map +-19.2 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] DRAM Controller \-19.3 Advanced Micro Devices, Inc. [AMD] K8 [Athlon64/Opteron] Miscellaneous Control - dmesg after ---------------------------------------------------------- [ 214.234819] pci_bus 0000:07: busn_res: [bus 07] is released [ 214.234981] pci_scan_child_bus: pci_bus 0000:00: scanning bus [ 214.235037] pci 0000:00:0a.0: [1166:0132] type 01 class 0x060400 [ 214.235128] pci 0000:00:0a.0: System wakeup disabled by ACPI [ 214.235221] pci_scan_bridge: pci 0000:00:01.0: scanning [bus 01-02] behind bridge, pass 0 [ 214.235227] pci_scan_child_bus: pci_bus 0000:01: scanning bus [ 214.235258] pci_scan_bridge: pci 0000:01:0d.0: scanning [bus 02-02] behind bridge, pass 0 [ 214.235262] pci_scan_child_bus: pci_bus 0000:02: scanning bus [ 214.235295] pci_scan_child_bus: pci_bus 0000:02: bus scan returning with max=02 [ 214.235301] pci_scan_bridge: pci 0000:01:0d.0: scanning [bus 02-02] behind bridge, pass 1 [ 214.235306] pci_scan_child_bus: pci_bus 0000:01: bus scan returning with max=02 [ 214.235312] pci_scan_bridge: pci 0000:00:06.0: scanning [bus 03-03] behind bridge, pass 0 [ 214.235316] pci_scan_child_bus: pci_bus 0000:03: scanning bus [ 214.235343] pci_scan_child_bus: pci_bus 0000:03: bus scan returning with max=03 [ 214.235348] pci_scan_bridge: pci 0000:00:07.0: scanning [bus 04-04] behind bridge, pass 0 [ 214.235352] pci_scan_child_bus: pci_bus 0000:04: scanning bus [ 214.235376] pci_scan_child_bus: pci_bus 0000:04: bus scan returning with max=04 [ 214.235381] pci_scan_bridge: pcieport 0000:00:08.0: scanning [bus 05-05] behind bridge, pass 0 [ 214.235386] pci_scan_child_bus: pci_bus 0000:05: scanning bus [ 214.235390] pci_scan_child_bus: pci_bus 0000:05: bus scan returning with max=05 [ 214.235394] pci_scan_bridge: pcieport 0000:00:09.0: scanning [bus 06-06] behind bridge, pass 0 [ 214.235398] pci_scan_child_bus: pci_bus 0000:06: scanning bus [ 214.235402] pci_scan_child_bus: pci_bus 0000:06: bus scan returning with max=06 [ 214.235407] pci_scan_bridge: pcieport 0000:00:0b.0: scanning [bus 08-08] behind bridge, pass 0 [ 214.235411] pci_scan_child_bus: pci_bus 0000:08: scanning bus [ 214.235415] pci_scan_child_bus: pci_bus 0000:08: bus scan returning with max=08 [ 214.235420] pci_scan_bridge: pci 0000:00:0a.0: scanning [bus 10-10] behind bridge, pass 0 [ 214.235457] pci_scan_child_bus: pci_bus 0000:10: scanning bus [ 214.235461] pci_scan_child_bus: pci_bus 0000:10: fixups for bus [ 214.235464] pci 0000:00:0a.0: PCI bridge to [bus 10] [ 214.235470] pci 0000:00:0a.0: bridge window [io 0x9000-0xbfff] [ 214.235475] pci 0000:00:0a.0: bridge window [mem 0xff300000-0xff5fffff] [ 214.235480] pci 0000:00:0a.0: bridge window [mem 0xcfe00000-0xcfefffff 64bit pref] [ 214.235483] pci_scan_child_bus: pci_bus 0000:10: bus scan returning with max=10 [ 214.235487] pci_scan_bridge: pci 0000:00:01.0: scanning [bus 01-02] behind bridge, pass 1 [ 214.235493] pci_scan_bridge: pci 0000:00:06.0: scanning [bus 03-03] behind bridge, pass 1 [ 214.235498] pci_scan_bridge: pci 0000:00:07.0: scanning [bus 04-04] behind bridge, pass 1 [ 214.235503] pci_scan_bridge: pcieport 0000:00:08.0: scanning [bus 05-05] behind bridge, pass 1 [ 214.235508] pci_scan_bridge: pcieport 0000:00:09.0: scanning [bus 06-06] behind bridge, pass 1 [ 214.235513] pci_scan_bridge: pcieport 0000:00:0b.0: scanning [bus 08-08] behind bridge, pass 1 [ 214.235518] pci_scan_bridge: pci 0000:00:0a.0: scanning [bus 10-10] behind bridge, pass 1 [ 214.235522] pci_scan_child_bus: pci_bus 0000:00: bus scan returning with max=10 [ 214.235567] pci 0000:00:0a.0: BAR 8: assigned [mem 0x80000000-0x802fffff] [ 214.235574] pci 0000:00:0a.0: BAR 9: assigned [mem 0x280000000-0x2800fffff 64bit pref] [ 214.235579] pci 0000:00:0a.0: BAR 7: assigned [io 0x1000-0x3fff] [ 214.235583] pci 0000:01:0d.0: PCI bridge to [bus 02] [ 214.235592] pci 0000:00:06.0: PCI bridge to [bus 03] [ 214.235599] pci 0000:00:0a.0: PCI bridge to [bus 10] [ 214.235603] pci 0000:00:0a.0: bridge window [io 0x1000-0x3fff] [ 214.235607] pci 0000:00:0a.0: bridge window [mem 0x80000000-0x802fffff] [ 214.235610] pci 0000:00:0a.0: bridge window [mem 0x280000000-0x2800fffff 64bit pref] [ 214.235622] fixup_debug_start: pci 0000:00:0a.0: calling quirk_msi_ht_cap+0x0/0x50 [ 214.235627] pci 0000:00:0a.0: Found enabled HT MSI Mapping [ 215.257656] pci_scan_child_bus: pci_bus 0000:00: scanning bus [ 215.257713] pci_scan_bridge: pci 0000:00:01.0: scanning [bus 01-02] behind bridge, pass 0 [ 215.257720] pci_scan_child_bus: pci_bus 0000:01: scanning bus [ 215.257750] pci_scan_bridge: pci 0000:01:0d.0: scanning [bus 02-02] behind bridge, pass 0 [ 215.257755] pci_scan_child_bus: pci_bus 0000:02: scanning bus [ 215.257788] pci_scan_child_bus: pci_bus 0000:02: bus scan returning with max=02 [ 215.257793] pci_scan_bridge: pci 0000:01:0d.0: scanning [bus 02-02] behind bridge, pass 1 [ 215.257798] pci_scan_child_bus: pci_bus 0000:01: bus scan returning with max=02 [ 215.257803] pci_scan_bridge: pci 0000:00:06.0: scanning [bus 03-03] behind bridge, pass 0 [ 215.257807] pci_scan_child_bus: pci_bus 0000:03: scanning bus [ 215.257834] pci_scan_child_bus: pci_bus 0000:03: bus scan returning with max=03 [ 215.257839] pci_scan_bridge: pci 0000:00:07.0: scanning [bus 04-04] behind bridge, pass 0 [ 215.257843] pci_scan_child_bus: pci_bus 0000:04: scanning bus [ 215.257867] pci_scan_child_bus: pci_bus 0000:04: bus scan returning with max=04 [ 215.257872] pci_scan_bridge: pcieport 0000:00:08.0: scanning [bus 05-05] behind bridge, pass 0 [ 215.257876] pci_scan_child_bus: pci_bus 0000:05: scanning bus [ 215.257880] pci_scan_child_bus: pci_bus 0000:05: bus scan returning with max=05 [ 215.257884] pci_scan_bridge: pcieport 0000:00:09.0: scanning [bus 06-06] behind bridge, pass 0 [ 215.257889] pci_scan_child_bus: pci_bus 0000:06: scanning bus [ 215.257893] pci_scan_child_bus: pci_bus 0000:06: bus scan returning with max=06 [ 215.257897] pci_scan_bridge: pcieport 0000:00:0b.0: scanning [bus 08-08] behind bridge, pass 0 [ 215.257901] pci_scan_child_bus: pci_bus 0000:08: scanning bus [ 215.257905] pci_scan_child_bus: pci_bus 0000:08: bus scan returning with max=08 [ 215.257910] pci_scan_bridge: pcieport 0000:00:0a.0: scanning [bus 10-10] behind bridge, pass 0 [ 215.257914] pci_scan_child_bus: pci_bus 0000:10: scanning bus [ 215.257918] pci_scan_child_bus: pci_bus 0000:10: bus scan returning with max=10 [ 215.257922] pci_scan_bridge: pci 0000:00:01.0: scanning [bus 01-02] behind bridge, pass 1 [ 215.257928] pci_scan_bridge: pci 0000:00:06.0: scanning [bus 03-03] behind bridge, pass 1 [ 215.257933] pci_scan_bridge: pci 0000:00:07.0: scanning [bus 04-04] behind bridge, pass 1 [ 215.257938] pci_scan_bridge: pcieport 0000:00:08.0: scanning [bus 05-05] behind bridge, pass 1 [ 215.257942] pci_scan_bridge: pcieport 0000:00:09.0: scanning [bus 06-06] behind bridge, pass 1 [ 215.257947] pci_scan_bridge: pcieport 0000:00:0b.0: scanning [bus 08-08] behind bridge, pass 1 [ 215.257952] pci_scan_bridge: pcieport 0000:00:0a.0: scanning [bus 10-10] behind bridge, pass 1 [ 215.257956] pci_scan_child_bus: pci_bus 0000:00: bus scan returning with max=10 [ 215.257994] pci 0000:01:0d.0: PCI bridge to [bus 02] [ 215.258033] pci 0000:00:06.0: PCI bridge to [bus 03] -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
From b504067748a1c0e4c4847fbb569c149b43d02904 Mon Sep 17 00:00:00 2001 From: Dirk Gouders <dirk@gouders.net> Date: Fri, 12 Sep 2014 21:20:38 +0200 Subject: [PATCH 2/4] PCI, pciehp: Use generic pcie_link_disable Also remove old version with not needed return check. Signed-off-by: Yinghai Lu <yinghai@kernel.org> --- drivers/pci/hotplug/pciehp_hpc.c | 30 +++--------------------------- 1 file changed, 3 insertions(+), 27 deletions(-) diff --git a/drivers/pci/hotplug/pciehp_hpc.c b/drivers/pci/hotplug/pciehp_hpc.c index 9da84b8..e8caa18 100644 --- a/drivers/pci/hotplug/pciehp_hpc.c +++ b/drivers/pci/hotplug/pciehp_hpc.c @@ -303,28 +303,6 @@ int pciehp_check_link_status(struct controller *ctrl) return 0; } -static int __pciehp_link_set(struct controller *ctrl, bool enable) -{ - struct pci_dev *pdev = ctrl_dev(ctrl); - u16 lnk_ctrl; - - pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &lnk_ctrl); - - if (enable) - lnk_ctrl &= ~PCI_EXP_LNKCTL_LD; - else - lnk_ctrl |= PCI_EXP_LNKCTL_LD; - - pcie_capability_write_word(pdev, PCI_EXP_LNKCTL, lnk_ctrl); - ctrl_dbg(ctrl, "%s: lnk_ctrl = %x\n", __func__, lnk_ctrl); - return 0; -} - -static int pciehp_link_enable(struct controller *ctrl) -{ - return __pciehp_link_set(ctrl, true); -} - void pciehp_get_attention_status(struct slot *slot, u8 *status) { struct controller *ctrl = slot->ctrl; @@ -471,7 +449,6 @@ int pciehp_power_on_slot(struct slot *slot) struct controller *ctrl = slot->ctrl; struct pci_dev *pdev = ctrl_dev(ctrl); u16 slot_status; - int retval; /* Clear sticky power-fault bit from previous power failures */ pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status); @@ -485,11 +462,10 @@ int pciehp_power_on_slot(struct slot *slot) pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, PCI_EXP_SLTCTL_PWR_ON); - retval = pciehp_link_enable(ctrl); - if (retval) - ctrl_err(ctrl, "%s: Can not enable the link!\n", __func__); + /* Enable the link */ + pcie_link_disable_set(ctrl->pcie->port, 0); - return retval; + return 0; } void pciehp_power_off_slot(struct slot *slot) -- 2.1.0