diff mbox series

PCI: pci-bridge-emul: fix array overruns, improve safety

Message ID E1l6z9W-0006Re-MQ@rmk-PC.armlinux.org.uk
State New
Headers show
Series PCI: pci-bridge-emul: fix array overruns, improve safety | expand

Commit Message

Russell King Feb. 2, 2021, 5:07 p.m. UTC
We allow up to PCI_EXP_SLTSTA2 registers to be accessed, but the
PCIe behaviour (pcie_cap_regs_behavior) array only covers up to
PCI_EXP_RTSTA. Expand this array to avoid walking off the end of it.

Do the same for pci_regs_behavior for consistency, and add a
BUILD_BUG_ON() to also check the bridge->conf structure size.

Fixes: 23a5fba4d941 ("PCI: Introduce PCI bridge emulated config space common logic")
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
---
 drivers/pci/pci-bridge-emul.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

Comments

Pali Rohár Feb. 3, 2021, 10:25 a.m. UTC | #1
On Tuesday 02 February 2021 17:07:46 Russell King wrote:
> We allow up to PCI_EXP_SLTSTA2 registers to be accessed, but the
> PCIe behaviour (pcie_cap_regs_behavior) array only covers up to
> PCI_EXP_RTSTA. Expand this array to avoid walking off the end of it.
> 
> Do the same for pci_regs_behavior for consistency, and add a
> BUILD_BUG_ON() to also check the bridge->conf structure size.
> 
> Fixes: 23a5fba4d941 ("PCI: Introduce PCI bridge emulated config space common logic")
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

Looks good!

Reviewed-by: Pali Rohár <pali@kernel.org>

Just to note that I'm planning to send a patch which adds missing
register definitions for pcie_cap_regs_behavior[].

> ---
>  drivers/pci/pci-bridge-emul.c | 11 ++++++++---
>  1 file changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
> index 139869d50eb2..fdaf86a888b7 100644
> --- a/drivers/pci/pci-bridge-emul.c
> +++ b/drivers/pci/pci-bridge-emul.c
> @@ -21,8 +21,9 @@
>  #include "pci-bridge-emul.h"
>  
>  #define PCI_BRIDGE_CONF_END	PCI_STD_HEADER_SIZEOF
> +#define PCI_CAP_PCIE_SIZEOF	(PCI_EXP_SLTSTA2 + 2)
>  #define PCI_CAP_PCIE_START	PCI_BRIDGE_CONF_END
> -#define PCI_CAP_PCIE_END	(PCI_CAP_PCIE_START + PCI_EXP_SLTSTA2 + 2)
> +#define PCI_CAP_PCIE_END	(PCI_CAP_PCIE_START + PCI_CAP_PCIE_SIZEOF)
>  
>  /**
>   * struct pci_bridge_reg_behavior - register bits behaviors
> @@ -46,7 +47,8 @@ struct pci_bridge_reg_behavior {
>  	u32 w1c;
>  };
>  
> -static const struct pci_bridge_reg_behavior pci_regs_behavior[] = {
> +static const
> +struct pci_bridge_reg_behavior pci_regs_behavior[PCI_STD_HEADER_SIZEOF / 4] = {
>  	[PCI_VENDOR_ID / 4] = { .ro = ~0 },
>  	[PCI_COMMAND / 4] = {
>  		.rw = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
> @@ -164,7 +166,8 @@ static const struct pci_bridge_reg_behavior pci_regs_behavior[] = {
>  	},
>  };
>  
> -static const struct pci_bridge_reg_behavior pcie_cap_regs_behavior[] = {
> +static const
> +struct pci_bridge_reg_behavior pcie_cap_regs_behavior[PCI_CAP_PCIE_SIZEOF / 4] = {
>  	[PCI_CAP_LIST_ID / 4] = {
>  		/*
>  		 * Capability ID, Next Capability Pointer and
> @@ -260,6 +263,8 @@ static const struct pci_bridge_reg_behavior pcie_cap_regs_behavior[] = {
>  int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
>  			 unsigned int flags)
>  {
> +	BUILD_BUG_ON(sizeof(bridge->conf) != PCI_BRIDGE_CONF_END);
> +
>  	bridge->conf.class_revision |= cpu_to_le32(PCI_CLASS_BRIDGE_PCI << 16);
>  	bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;
>  	bridge->conf.cache_line_size = 0x10;
> -- 
> 2.20.1
>
Bjorn Helgaas Feb. 17, 2021, 11:30 p.m. UTC | #2
On Tue, Feb 02, 2021 at 05:07:46PM +0000, Russell King wrote:
> We allow up to PCI_EXP_SLTSTA2 registers to be accessed, but the
> PCIe behaviour (pcie_cap_regs_behavior) array only covers up to
> PCI_EXP_RTSTA. Expand this array to avoid walking off the end of it.
> 
> Do the same for pci_regs_behavior for consistency, and add a
> BUILD_BUG_ON() to also check the bridge->conf structure size.
> 
> Fixes: 23a5fba4d941 ("PCI: Introduce PCI bridge emulated config space common logic")
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

Applied with Pali's Reviewed-by to pci/enumeration for v5.12, thanks!

> ---
>  drivers/pci/pci-bridge-emul.c | 11 ++++++++---
>  1 file changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
> index 139869d50eb2..fdaf86a888b7 100644
> --- a/drivers/pci/pci-bridge-emul.c
> +++ b/drivers/pci/pci-bridge-emul.c
> @@ -21,8 +21,9 @@
>  #include "pci-bridge-emul.h"
>  
>  #define PCI_BRIDGE_CONF_END	PCI_STD_HEADER_SIZEOF
> +#define PCI_CAP_PCIE_SIZEOF	(PCI_EXP_SLTSTA2 + 2)
>  #define PCI_CAP_PCIE_START	PCI_BRIDGE_CONF_END
> -#define PCI_CAP_PCIE_END	(PCI_CAP_PCIE_START + PCI_EXP_SLTSTA2 + 2)
> +#define PCI_CAP_PCIE_END	(PCI_CAP_PCIE_START + PCI_CAP_PCIE_SIZEOF)
>  
>  /**
>   * struct pci_bridge_reg_behavior - register bits behaviors
> @@ -46,7 +47,8 @@ struct pci_bridge_reg_behavior {
>  	u32 w1c;
>  };
>  
> -static const struct pci_bridge_reg_behavior pci_regs_behavior[] = {
> +static const
> +struct pci_bridge_reg_behavior pci_regs_behavior[PCI_STD_HEADER_SIZEOF / 4] = {
>  	[PCI_VENDOR_ID / 4] = { .ro = ~0 },
>  	[PCI_COMMAND / 4] = {
>  		.rw = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
> @@ -164,7 +166,8 @@ static const struct pci_bridge_reg_behavior pci_regs_behavior[] = {
>  	},
>  };
>  
> -static const struct pci_bridge_reg_behavior pcie_cap_regs_behavior[] = {
> +static const
> +struct pci_bridge_reg_behavior pcie_cap_regs_behavior[PCI_CAP_PCIE_SIZEOF / 4] = {
>  	[PCI_CAP_LIST_ID / 4] = {
>  		/*
>  		 * Capability ID, Next Capability Pointer and
> @@ -260,6 +263,8 @@ static const struct pci_bridge_reg_behavior pcie_cap_regs_behavior[] = {
>  int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
>  			 unsigned int flags)
>  {
> +	BUILD_BUG_ON(sizeof(bridge->conf) != PCI_BRIDGE_CONF_END);
> +
>  	bridge->conf.class_revision |= cpu_to_le32(PCI_CLASS_BRIDGE_PCI << 16);
>  	bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;
>  	bridge->conf.cache_line_size = 0x10;
> -- 
> 2.20.1
>
diff mbox series

Patch

diff --git a/drivers/pci/pci-bridge-emul.c b/drivers/pci/pci-bridge-emul.c
index 139869d50eb2..fdaf86a888b7 100644
--- a/drivers/pci/pci-bridge-emul.c
+++ b/drivers/pci/pci-bridge-emul.c
@@ -21,8 +21,9 @@ 
 #include "pci-bridge-emul.h"
 
 #define PCI_BRIDGE_CONF_END	PCI_STD_HEADER_SIZEOF
+#define PCI_CAP_PCIE_SIZEOF	(PCI_EXP_SLTSTA2 + 2)
 #define PCI_CAP_PCIE_START	PCI_BRIDGE_CONF_END
-#define PCI_CAP_PCIE_END	(PCI_CAP_PCIE_START + PCI_EXP_SLTSTA2 + 2)
+#define PCI_CAP_PCIE_END	(PCI_CAP_PCIE_START + PCI_CAP_PCIE_SIZEOF)
 
 /**
  * struct pci_bridge_reg_behavior - register bits behaviors
@@ -46,7 +47,8 @@  struct pci_bridge_reg_behavior {
 	u32 w1c;
 };
 
-static const struct pci_bridge_reg_behavior pci_regs_behavior[] = {
+static const
+struct pci_bridge_reg_behavior pci_regs_behavior[PCI_STD_HEADER_SIZEOF / 4] = {
 	[PCI_VENDOR_ID / 4] = { .ro = ~0 },
 	[PCI_COMMAND / 4] = {
 		.rw = (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
@@ -164,7 +166,8 @@  static const struct pci_bridge_reg_behavior pci_regs_behavior[] = {
 	},
 };
 
-static const struct pci_bridge_reg_behavior pcie_cap_regs_behavior[] = {
+static const
+struct pci_bridge_reg_behavior pcie_cap_regs_behavior[PCI_CAP_PCIE_SIZEOF / 4] = {
 	[PCI_CAP_LIST_ID / 4] = {
 		/*
 		 * Capability ID, Next Capability Pointer and
@@ -260,6 +263,8 @@  static const struct pci_bridge_reg_behavior pcie_cap_regs_behavior[] = {
 int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
 			 unsigned int flags)
 {
+	BUILD_BUG_ON(sizeof(bridge->conf) != PCI_BRIDGE_CONF_END);
+
 	bridge->conf.class_revision |= cpu_to_le32(PCI_CLASS_BRIDGE_PCI << 16);
 	bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;
 	bridge->conf.cache_line_size = 0x10;