From patchwork Fri Apr 13 06:46:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinath Mannam X-Patchwork-Id: 897862 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=quarantine dis=none) header.from=broadcom.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=broadcom.com header.i=@broadcom.com header.b="OYRSKYxU"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 40MpGd5zHJz9s16 for ; Fri, 13 Apr 2018 16:46:49 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1750857AbeDMGqr (ORCPT ); Fri, 13 Apr 2018 02:46:47 -0400 Received: from mail-ot0-f194.google.com ([74.125.82.194]:34270 "EHLO mail-ot0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750761AbeDMGqr (ORCPT ); Fri, 13 Apr 2018 02:46:47 -0400 Received: by mail-ot0-f194.google.com with SMTP id m7-v6so8787825otd.1 for ; Thu, 12 Apr 2018 23:46:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=broadcom.com; s=google; h=mime-version:from:date:message-id:subject:to:cc; bh=Ez643sONBKtWoJ9oVqRNUMjg1LviWkYXMnnY17V2i5s=; b=OYRSKYxUtakyQGd64N8qJhCT39ZsoNV7paSWHCcLncovhjhVv17429VfMKW2DEzdat j1qL3niB+NLd0xuiYX+UkM0YIcQY02ATxQLDLNE+T9E5lQxQaH2wFUQNmFoYTLtILbXH +4pNcuA8JxizyCNFmJNNuQY/RQKGJKsUAtlJU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:from:date:message-id:subject:to:cc; bh=Ez643sONBKtWoJ9oVqRNUMjg1LviWkYXMnnY17V2i5s=; b=ZPOOvC84fFVotCBgBuU+dp39i6oQzfUGR+5iQ5zMPs9y1Qzo4ekB233WEHnAlCdsjz 1VSsbqe0BZaTAF/1qxqDIUM5kCqj0oJjfkyi3DwJ/lh+g7DGLc15T5JS1Zl+Clltrabd I7ifmr1q2svUyY48BSUSXWhDX6eJXoeh9yHYQ/wCpsExiRyHmvWK/82S/IzOKRlCjTPz yVtZtzr+QPiXqIVuETlUNEjIElFwkiMww+jWigQYCe66NeY73QWXcLQ8MFDtfTKlsOQV qHIWTCNU4dFG9omr3vlkCtTiTnBIfVu/z8yvIZJoTXRaaHU8aQlSoOXw5i18uqt5BXta K1Mw== X-Gm-Message-State: ALQs6tDpWbih0kCTS4M0/LNpNXUTfCalkTLiEPaVNQ8L5/3X/MpKw1dP hW1SRpuEUUGTw7jehhnUUmUVMS81PAgCqRR+OAqBwA== X-Google-Smtp-Source: AIpwx4/TtI9v6KYbhwIENiI5a7PEl12NdZXpI0cdqpnJbIHjG6JpkujQSSOC4yAUJwKKQa8p6N/kL4oRS7+Jfa8Sc2E= X-Received: by 2002:a9d:38a2:: with SMTP id p31-v6mr2529639otc.299.1523602006659; Thu, 12 Apr 2018 23:46:46 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a9d:4d13:0:0:0:0:0 with HTTP; Thu, 12 Apr 2018 23:46:46 -0700 (PDT) From: Srinath Mannam Date: Fri, 13 Apr 2018 12:16:46 +0530 Message-ID: Subject: Issue with Enable LTR while pcie_aspm off To: Bjorn Helgaas Cc: Ray Jui , linux-pci@vger.kernel.org Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Hi Bjorn, In our platform we disable aspm using boot_arg "pcie_aspm=off". But with the below patch, LTR is enabled which is part of ASPM. even we keep disable aspm using "pcie_aspm=off" then why we need to enable LTR. This is causing issues with few NVMe cards. Please advice us how can we proceed in this scenario. commit c46fd358070f22ba68d6e74c22016a33b914c20a Author: Bjorn Helgaas Date: Tue Nov 28 16:43:50 2017 -0600 PCI/ASPM: Enable Latency Tolerance Reporting when supported Enable Latency Tolerance Reporting (LTR). Note that LTR must be enabled in the Root Port first, and must not be enabled in any downstream device unless the Root Port and all intermediate Switches also support LTR. See PCIe r3.1, sec 6.18. Signed-off-by: Bjorn Helgaas Reviewed-by: Vidya Sagar struct hotplug_params hpp; @@ -1883,6 +1915,7 @@ static void pci_configure_device(struct pci_dev *dev) pci_configure_mps(dev); pci_configure_extended_tags(dev, NULL); pci_configure_relaxed_ordering(dev); Regards, Srinath. diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c index 14e0ea1..3761b13 100644 --- a/drivers/pci/probe.c +++ b/drivers/pci/probe.c @@ -1875,6 +1875,38 @@ static void pci_configure_relaxed_ordering(struct pci_dev *dev) } } +static void pci_configure_ltr(struct pci_dev *dev) +{ +#ifdef CONFIG_PCIEASPM + u32 cap; + struct pci_dev *bridge; + + if (!pci_is_pcie(dev)) + return; + + pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); + if (!(cap & PCI_EXP_DEVCAP2_LTR)) + return; + + /* + * Software must not enable LTR in an Endpoint unless the Root + * Complex and all intermediate Switches indicate support for LTR. + * PCIe r3.1, sec 6.18. + */ + if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) + dev->ltr_path = 1; + else { + bridge = pci_upstream_bridge(dev); + if (bridge && bridge->ltr_path) + dev->ltr_path = 1; + } + + if (dev->ltr_path) + pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, + PCI_EXP_DEVCTL2_LTR_EN); +#endif +} + static void pci_configure_device(struct pci_dev *dev) {