@@ -442,6 +442,7 @@ int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
int pci_aer_clear_err_uncor_status(struct pci_dev *dev);
void pci_aer_clear_err_fatal_status(struct pci_dev *dev);
+int pci_aer_clear_err_status_regs(struct pci_dev *dev);
#endif /* CONFIG_PCIEAER */
#ifdef CONFIG_PCIE_DPC
@@ -431,7 +431,7 @@ void pci_aer_clear_fatal_status(struct pci_dev *dev)
return pci_aer_clear_err_fatal_status(dev);
}
-int pci_cleanup_aer_error_status_regs(struct pci_dev *dev)
+int pci_aer_clear_err_status_regs(struct pci_dev *dev)
{
int pos;
u32 status;
@@ -444,9 +444,6 @@ int pci_cleanup_aer_error_status_regs(struct pci_dev *dev)
if (!pos)
return -EIO;
- if (pcie_aer_get_firmware_first(dev))
- return -EIO;
-
port_type = pci_pcie_type(dev);
if (port_type == PCI_EXP_TYPE_ROOT_PORT) {
pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &status);
@@ -462,6 +459,14 @@ int pci_cleanup_aer_error_status_regs(struct pci_dev *dev)
return 0;
}
+int pci_cleanup_aer_error_status_regs(struct pci_dev *dev)
+{
+ if (pcie_aer_get_firmware_first(dev))
+ return -EIO;
+
+ return pci_aer_clear_err_status_regs(dev);
+}
+
void pci_save_aer_state(struct pci_dev *dev)
{
struct pci_cap_saved_state *save_state;
@@ -284,6 +284,10 @@ static void dpc_process_error(struct dpc_dev *dpc)
pci_aer_clear_err_fatal_status(pdev);
}
+ /* In EDR mode, OS is responsible for clearing AER registers */
+ if (dpc->edr_enabled)
+ pci_aer_clear_err_status_regs(pdev);
+
/*
* Irrespective of whether the DPC event is triggered by
* ERR_FATAL or ERR_NONFATAL, since the link is already down,