diff mbox series

PCI: Change CLS info in pci_apply_final_quirks to debug level

Message ID 785a8518-cdcb-a3e1-add6-6c8964b46bf7@gmail.com
State New
Headers show
Series PCI: Change CLS info in pci_apply_final_quirks to debug level | expand

Commit Message

Heiner Kallweit Dec. 9, 2020, 2 p.m. UTC
CLS is relevant only for devices using MWI, in addition
not really helpful messages like the following are printed:
PCI: CLS 0 bytes, default 64
Therefore change CLS info to debug level.

Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
---
 drivers/pci/quirks.c | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)
diff mbox series

Patch

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index d9cbe69b8..af8d8ddfe 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -157,9 +157,6 @@  static int __init pci_apply_final_quirks(void)
 	u8 cls = 0;
 	u8 tmp;
 
-	if (pci_cache_line_size)
-		pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2);
-
 	pci_apply_fixup_final_quirks = true;
 	for_each_pci_dev(dev) {
 		pci_fixup_device(pci_fixup_final, dev);
@@ -182,11 +179,11 @@  static int __init pci_apply_final_quirks(void)
 		}
 	}
 
-	if (!pci_cache_line_size) {
-		pr_info("PCI: CLS %u bytes, default %u\n", cls << 2,
-			pci_dfl_cache_line_size << 2);
-		pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
-	}
+	if (!pci_cache_line_size)
+		pci_cache_line_size = cls ?: pci_dfl_cache_line_size;
+
+	pr_debug("PCI: CLS %u bytes, default %u\n", pci_cache_line_size << 2,
+		 pci_dfl_cache_line_size << 2);
 
 	return 0;
 }