| Message ID | 67aa2c189337181bb2d7721fb616db5640587d2a.1624454607.git.michal.simek@xilinx.com |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: xilinx-nwl: Add clock handling | expand |
diff --git a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt index 2d677e90a7e2..f56f8c58c5d9 100644 --- a/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt +++ b/Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt @@ -35,6 +35,7 @@ Required properties: Optional properties: - dma-coherent: present if DMA operations are coherent +- clocks: Input clock specifier. Refer to common clock bindings Example: ++++++++
Clock property hasn't been documented in binding document but it is used for quite a long time where clock was specified by commit 9c8a47b484ed ("arm64: dts: xilinx: Add the clock nodes for zynqmp"). Signed-off-by: Michal Simek <michal.simek@xilinx.com> --- Changes in v2: - new patch in this series because I found that it has never been sent Bharat: Can you please start to work on converting it to yaml? --- Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt | 1 + 1 file changed, 1 insertion(+)