diff mbox series

[v2,03/11] doc: bindings: add new parameters used by Kirin 970

Message ID 4d081ef108091aefd46cd7a520a63b94d2911f90.1612335031.git.mchehab+huawei@kernel.org
State New
Headers show
Series Add support for Hikey 970 PCIe | expand

Commit Message

Mauro Carvalho Chehab Feb. 3, 2021, 7:01 a.m. UTC
There are a few extra optional bindings that are needed for Kirin 970
based PCIe designs to work. Add them.

Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
 .../bindings/pci/hisilicon,kirin-pcie.yaml    | 60 ++++++++++++++++++-
 1 file changed, 57 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
index 46f9f3f25dbc..7a58883e07ec 100644
--- a/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
@@ -34,8 +34,18 @@  properties:
       - const: config       # PCIe configuration space registers
 
   reset-gpios:
-    description: The GPIO to generate PCIe PERST# assert and deassert signal.
-    maxItems: 1
+    description: The GPIOs to generate PCIe PERST# assert and deassert signal.
+    minItems: 1
+    maxItems: 4
+
+  clkreq-gpios:
+    description: CLKREQ signal GPIO pins to be enabled during PCI power on
+    minItems: 1
+    maxItems: 3
+
+  eye_param:
+    description: items to adjust the eye parameters
+    maxItems: 5
 
 required:
   - compatible
@@ -52,12 +62,13 @@  examples:
   - |
     #include <dt-bindings/interrupt-controller/arm-gic.h>
     #include <dt-bindings/clock/hi3660-clock.h>
+    #include <dt-bindings/clock/hi3670-clock.h>
 
     soc {
       #address-cells = <2>;
       #size-cells = <2>;
 
-      pcie: pcie@f4000000 {
+      pcie1: pcie@f4000000 {
         compatible = "hisilicon,kirin960-pcie";
         reg = <0x0 0xf4000000 0x0 0x1000>,
               <0x0 0xff3fe000 0x0 0x1000>,
@@ -87,4 +98,47 @@  examples:
                       "pcie_apb_sys", "pcie_aclk";
         reset-gpios = <&gpio11 1 0 >;
       };
+
+      pcie2: pcie@f5000000 {
+        compatible = "hisilicon,kirin970-pcie";
+        reg = <0x0 0xf4000000 0x0 0x1000000>,
+              <0x0 0xfc180000 0x0 0x1000>,
+              <0x0 0xfc000000 0x0 0x80000>,
+              <0x0 0xf5000000 0x0 0x2000>;
+        pci-supply = <&ldo33>;
+        reg-names = "dbi", "apb", "phy", "config";
+        bus-range = <0x0  0x1>;
+        #address-cells = <3>;
+        #size-cells = <2>;
+        device_type = "pci";
+        ranges = <0x02000000 0x0 0x00000000 0x0 0xf6000000 0x0 0x02000000>;
+        num-lanes = <1>;
+        #interrupt-cells = <1>;
+        interrupts = <0 283 4>;
+        interrupt-names = "msi";
+        interrupt-map-mask = <0 0 0 7>;
+        interrupt-map = <0x0 0 0 1 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x0 0 0 2 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x0 0 0 3 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+                        <0x0 0 0 4 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+        clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>,
+                 <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>,
+                 <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>,
+                 <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>,
+                 <&crg_ctrl HI3670_ACLK_GATE_PCIE>;
+
+        clock-names = "pcie_phy_ref", "pcie_aux",
+                      "pcie_apb_phy", "pcie_apb_sys",
+                      "pcie_aclk";
+        reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >,
+                      <&gpio3 1 0 >, <&gpio27 4 0 >;
+
+        clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >, <&gpio17 0 0 >;
+
+        /* vboost iboost pre post main */
+        eye_param = <0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF 0xFFFFFFFF>;
+        msi-parent = <&its_pcie>;
+        pinctrl-names = "default";
+        pinctrl-0 = <&pcie_clkreq_pmx_func &pcie_clkreq_cfg_func>;
+      };
     };