| Message ID | 3b43f37cc5fe654294c1ea696ed8df1797ad213b.1531155252.git.gustavo.pimentel@synopsys.com |
|---|---|
| State | Superseded |
| Delegated to: | Lorenzo Pieralisi |
| Headers | show |
| Series | Add MSI-X support on pcitest tool | expand |
On Monday 09 July 2018 11:12 PM, Gustavo Pimentel wrote: > Move specific features settings from EP shared code > (pcie-designware-ep.c) to the driver (pcie-designware-plat.c). > > Previous implementation disables the EP link notification > by default for all SoCs that uses EP DesignWare IP, which affects > directly the dra7xx and artpec6 SoCs. > > Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> Acked-by: Kishon Vijay Abraham I <kishon@ti.com> > --- > Change v8->v9: > - Created patch file. > > drivers/pci/controller/dwc/pcie-designware-ep.c | 14 ++++++-------- > drivers/pci/controller/dwc/pcie-designware-plat.c | 3 +++ > 2 files changed, 9 insertions(+), 8 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c > index 8650416..04092a7 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-ep.c > +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c > @@ -386,15 +386,18 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) > return -ENOMEM; > ep->outbound_addr = addr; > > - if (ep->ops->ep_init) > - ep->ops->ep_init(ep); > - > epc = devm_pci_epc_create(dev, &epc_ops); > if (IS_ERR(epc)) { > dev_err(dev, "Failed to create epc device\n"); > return PTR_ERR(epc); > } > > + ep->epc = epc; > + epc_set_drvdata(epc, ep); > + > + if (ep->ops->ep_init) > + ep->ops->ep_init(ep); > + > ret = of_property_read_u8(np, "max-functions", &epc->max_functions); > if (ret < 0) > epc->max_functions = 1; > @@ -413,11 +416,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) > return -ENOMEM; > } > > - epc->features = EPC_FEATURE_NO_LINKUP_NOTIFIER; > - EPC_FEATURE_SET_BAR(epc->features, BAR_0); > - > - ep->epc = epc; > - epc_set_drvdata(epc, ep); > dw_pcie_setup(pci); > > return 0; > diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c > index 5937fed..0ce3440 100644 > --- a/drivers/pci/controller/dwc/pcie-designware-plat.c > +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c > @@ -70,10 +70,13 @@ static const struct dw_pcie_ops dw_pcie_ops = { > static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep) > { > struct dw_pcie *pci = to_dw_pcie_from_ep(ep); > + struct pci_epc *epc = ep->epc; > enum pci_barno bar; > > for (bar = BAR_0; bar <= BAR_5; bar++) > dw_pcie_ep_reset_bar(pci, bar); > + > + epc->features |= EPC_FEATURE_NO_LINKUP_NOTIFIER; > } > > static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, >
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 8650416..04092a7 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -386,15 +386,18 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) return -ENOMEM; ep->outbound_addr = addr; - if (ep->ops->ep_init) - ep->ops->ep_init(ep); - epc = devm_pci_epc_create(dev, &epc_ops); if (IS_ERR(epc)) { dev_err(dev, "Failed to create epc device\n"); return PTR_ERR(epc); } + ep->epc = epc; + epc_set_drvdata(epc, ep); + + if (ep->ops->ep_init) + ep->ops->ep_init(ep); + ret = of_property_read_u8(np, "max-functions", &epc->max_functions); if (ret < 0) epc->max_functions = 1; @@ -413,11 +416,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) return -ENOMEM; } - epc->features = EPC_FEATURE_NO_LINKUP_NOTIFIER; - EPC_FEATURE_SET_BAR(epc->features, BAR_0); - - ep->epc = epc; - epc_set_drvdata(epc, ep); dw_pcie_setup(pci); return 0; diff --git a/drivers/pci/controller/dwc/pcie-designware-plat.c b/drivers/pci/controller/dwc/pcie-designware-plat.c index 5937fed..0ce3440 100644 --- a/drivers/pci/controller/dwc/pcie-designware-plat.c +++ b/drivers/pci/controller/dwc/pcie-designware-plat.c @@ -70,10 +70,13 @@ static const struct dw_pcie_ops dw_pcie_ops = { static void dw_plat_pcie_ep_init(struct dw_pcie_ep *ep) { struct dw_pcie *pci = to_dw_pcie_from_ep(ep); + struct pci_epc *epc = ep->epc; enum pci_barno bar; for (bar = BAR_0; bar <= BAR_5; bar++) dw_pcie_ep_reset_bar(pci, bar); + + epc->features |= EPC_FEATURE_NO_LINKUP_NOTIFIER; } static int dw_plat_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
Move specific features settings from EP shared code (pcie-designware-ep.c) to the driver (pcie-designware-plat.c). Previous implementation disables the EP link notification by default for all SoCs that uses EP DesignWare IP, which affects directly the dra7xx and artpec6 SoCs. Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com> --- Change v8->v9: - Created patch file. drivers/pci/controller/dwc/pcie-designware-ep.c | 14 ++++++-------- drivers/pci/controller/dwc/pcie-designware-plat.c | 3 +++ 2 files changed, 9 insertions(+), 8 deletions(-)