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27 May 2024 02:37:56 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.35; Mon, 27 May 2024 02:37:50 -0700 Received: from wendy.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Mon, 27 May 2024 02:37:48 -0700 From: Conor Dooley To: CC: , , Daire McNamara , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , , , , Subject: [PATCH v1 1/2] dt-bindings: PCI: microchip,pcie-host: fix reg properties Date: Mon, 27 May 2024 10:37:15 +0100 Message-ID: <20240527-algebra-pencil-c12962d62468@wendy> X-Mailer: git-send-email 2.43.2 In-Reply-To: <20240527-slather-backfire-db4605ae7cd7@wendy> References: <20240527-slather-backfire-db4605ae7cd7@wendy> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2214; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=jLxBnH+agZ/3F1Kw1anar+d5wkAwz2H+nxCeoMbZaQk=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDGkhId5rFl7rj1DlMDmXwiPHdV7lwN79ahr/jjs7Gtkc1LqZ 91avo5SFQYyDQVZMkSXxdl+L1Po/Ljuce97CzGFlAhnCwMUpABNJyWVk2PokpSn/VlUO36XrwnFqm6 aw/S2MWiX2SPFiWN+MgrMSRgz/c4RLlV7s2LeQ9e3dbyfanE6c8WXq41WtqbBw3Ht4+RMWRgA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C The PCI host controller on PolarFire SoC has multiple "instances", each with their own bridge and ctrl address spaces. The original binding has an "apb" register region, and it is expected to be set to the base address of the host controllers register space. Some defines in the Linux driver were used to compute the addresses of the bridge and ctrl address ranges corresponding to instance1. Some customers want to use instance2 however and that requires changing the defines in the driver, which is clearly not a portable solution. Remove this "apb" register region from the binding and add "bridge" & "ctrl" regions instead, that will directly communicate the address of these regions Fixes: 6ee6c89aac35 ("dt-bindings: PCI: microchip: Add Microchip PolarFire host binding") Signed-off-by: Conor Dooley Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/pci/microchip,pcie-host.yaml | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml index 5d7aec5f54e71..45c14b6e4aa41 100644 --- a/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml @@ -18,12 +18,13 @@ properties: const: microchip,pcie-host-1.0 # PolarFire reg: - maxItems: 2 + maxItems: 3 reg-names: items: - const: cfg - - const: apb + - const: bridge + - const: ctrl clocks: description: @@ -115,8 +116,9 @@ examples: pcie0: pcie@2030000000 { compatible = "microchip,pcie-host-1.0"; reg = <0x0 0x70000000 0x0 0x08000000>, - <0x0 0x43000000 0x0 0x00010000>; - reg-names = "cfg", "apb"; + <0x0 0x43008000 0x0 0x00002000>, + <0x0 0x4300a000 0x0 0x00002000>; + reg-names = "cfg", "bridge", "ctrl"; device_type = "pci"; #address-cells = <3>; #size-cells = <2>;