| Message ID | 20240430-rockchip-pcie-ep-v1-v2-14-a0f5ee2a77b6@kernel.org |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: dw-rockchip: Add endpoint mode support | expand |
On Tue, Apr 30, 2024 at 02:01:11PM +0200, Niklas Cassel wrote: > Add rock5b overlays for PCIe endpoint mode support. > I'm not aware of mainline using overlays. Is this a new one? - Mani > If using the rock5b as an endpoint against a normal PC, only the > rk3588-rock-5b-pcie-ep.dtbo needs to be applied. > > If using two rock5b:s, with one board as EP and the other board as RC, > rk3588-rock-5b-pcie-ep.dtbo and rk3588-rock-5b-pcie-srns.dtbo has to > be applied to the respective boards. > > Signed-off-by: Niklas Cassel <cassel@kernel.org> > --- > arch/arm64/boot/dts/rockchip/Makefile | 5 +++++ > .../boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso | 25 ++++++++++++++++++++++ > .../dts/rockchip/rk3588-rock-5b-pcie-srns.dtso | 16 ++++++++++++++ > 3 files changed, 46 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile > index f906a868b71a..d827432d5111 100644 > --- a/arch/arm64/boot/dts/rockchip/Makefile > +++ b/arch/arm64/boot/dts/rockchip/Makefile > @@ -117,6 +117,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-quartzpro64.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb > +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo > +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb > @@ -127,3 +129,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb > + > +# Enable support for device-tree overlays > +DTC_FLAGS_rk3588-rock-5b += -@ > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso > new file mode 100644 > index 000000000000..672d748fcc67 > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso > @@ -0,0 +1,25 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * DT-overlay to run the PCIe3_4L Dual Mode controller in Endpoint mode > + * in the SRNS (Separate Reference Clock No Spread) configuration. > + * > + * NOTE: If using a setup with two ROCK 5B:s, with one board running in > + * RC mode and the other board running in EP mode, see also the device > + * tree overlay: rk3588-rock-5b-pcie-srns.dtso. > + */ > + > +/dts-v1/; > +/plugin/; > + > +&pcie30phy { > + rockchip,rx-common-refclk-mode = <0 0 0 0>; > +}; > + > +&pcie3x4 { > + status = "disabled"; > +}; > + > +&pcie3x4_ep { > + vpcie3v3-supply = <&vcc3v3_pcie30>; > + status = "okay"; > +}; > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso > new file mode 100644 > index 000000000000..1a0f1af65c43 > --- /dev/null > +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso > @@ -0,0 +1,16 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * DT-overlay to run the PCIe3_4L Dual Mode controller in Root Complex > + * mode in the SRNS (Separate Reference Clock No Spread) configuration. > + * > + * This device tree overlay is only needed (on the RC side) when running > + * a setup with two ROCK 5B:s, with one board running in RC mode and the > + * other board running in EP mode. > + */ > + > +/dts-v1/; > +/plugin/; > + > +&pcie30phy { > + rockchip,rx-common-refclk-mode = <0 0 0 0>; > +}; > > -- > 2.44.0 >
Am Samstag, 4. Mai 2024, 19:37:30 CEST schrieb Manivannan Sadhasivam: > On Tue, Apr 30, 2024 at 02:01:11PM +0200, Niklas Cassel wrote: > > Add rock5b overlays for PCIe endpoint mode support. > > > > I'm not aware of mainline using overlays. Is this a new one? I guess you could still call it new'ish ;-) But the mainline kernel does carry a number of overlays already [0] . This does of course not handle the actual application of overlays, which I guess bootloaders do only at this point. But I think it's definitely reasonable to carry them in a "central" location especially as for example u-boot uses the kernel as canonical source for most of its devicetrees. Heikoi [0] some random examples ;-) https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/amlogic/meson-g12a-fbx8am-realtek.dtso https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-wifi.dtso > > If using the rock5b as an endpoint against a normal PC, only the > > rk3588-rock-5b-pcie-ep.dtbo needs to be applied. > > > > If using two rock5b:s, with one board as EP and the other board as RC, > > rk3588-rock-5b-pcie-ep.dtbo and rk3588-rock-5b-pcie-srns.dtbo has to > > be applied to the respective boards. > > > > Signed-off-by: Niklas Cassel <cassel@kernel.org> > > --- > > arch/arm64/boot/dts/rockchip/Makefile | 5 +++++ > > .../boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso | 25 ++++++++++++++++++++++ > > .../dts/rockchip/rk3588-rock-5b-pcie-srns.dtso | 16 ++++++++++++++ > > 3 files changed, 46 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile > > index f906a868b71a..d827432d5111 100644 > > --- a/arch/arm64/boot/dts/rockchip/Makefile > > +++ b/arch/arm64/boot/dts/rockchip/Makefile > > @@ -117,6 +117,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-quartzpro64.dtb > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb > > +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo > > +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb > > @@ -127,3 +129,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb > > + > > +# Enable support for device-tree overlays > > +DTC_FLAGS_rk3588-rock-5b += -@ > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso > > new file mode 100644 > > index 000000000000..672d748fcc67 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso > > @@ -0,0 +1,25 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > +/* > > + * DT-overlay to run the PCIe3_4L Dual Mode controller in Endpoint mode > > + * in the SRNS (Separate Reference Clock No Spread) configuration. > > + * > > + * NOTE: If using a setup with two ROCK 5B:s, with one board running in > > + * RC mode and the other board running in EP mode, see also the device > > + * tree overlay: rk3588-rock-5b-pcie-srns.dtso. > > + */ > > + > > +/dts-v1/; > > +/plugin/; > > + > > +&pcie30phy { > > + rockchip,rx-common-refclk-mode = <0 0 0 0>; > > +}; > > + > > +&pcie3x4 { > > + status = "disabled"; > > +}; > > + > > +&pcie3x4_ep { > > + vpcie3v3-supply = <&vcc3v3_pcie30>; > > + status = "okay"; > > +}; > > diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso > > new file mode 100644 > > index 000000000000..1a0f1af65c43 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso > > @@ -0,0 +1,16 @@ > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > +/* > > + * DT-overlay to run the PCIe3_4L Dual Mode controller in Root Complex > > + * mode in the SRNS (Separate Reference Clock No Spread) configuration. > > + * > > + * This device tree overlay is only needed (on the RC side) when running > > + * a setup with two ROCK 5B:s, with one board running in RC mode and the > > + * other board running in EP mode. > > + */ > > + > > +/dts-v1/; > > +/plugin/; > > + > > +&pcie30phy { > > + rockchip,rx-common-refclk-mode = <0 0 0 0>; > > +}; > > > >
On Sun, May 05, 2024 at 02:14:45PM +0200, Heiko Stübner wrote: > Am Samstag, 4. Mai 2024, 19:37:30 CEST schrieb Manivannan Sadhasivam: > > On Tue, Apr 30, 2024 at 02:01:11PM +0200, Niklas Cassel wrote: > > > Add rock5b overlays for PCIe endpoint mode support. > > > > > > > I'm not aware of mainline using overlays. Is this a new one? > > I guess you could still call it new'ish ;-) > > But the mainline kernel does carry a number of overlays already [0] . > This does of course not handle the actual application of overlays, > which I guess bootloaders do only at this point. Yes, AFAICT, the actual application is handled by bootloaders. (Well, there is a "Overlay in-kernel API", but not a user API.) > > > diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile > > > index f906a868b71a..d827432d5111 100644 > > > --- a/arch/arm64/boot/dts/rockchip/Makefile > > > +++ b/arch/arm64/boot/dts/rockchip/Makefile > > > @@ -117,6 +117,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-quartzpro64.dtb > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb > > > +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo > > > +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb > > > @@ -127,3 +129,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb > > > + > > > +# Enable support for device-tree overlays > > > +DTC_FLAGS_rk3588-rock-5b += -@ Note that this DTC compiler flag is needed for the overlay for the bootloader to be able to apply the overlay successfully. (In order to supply the .dtbo compiled by the kernel directly to u-boot.) I'm not sure how the other rockchip overlays compiled by the kernel can work when suppling them to u-boot. I'm guessing that they compile them externally/manually outside the source tree with the -@ flag enabled. If we look at other arm64 device tree overlays in the kernel, e.g. TI, they seem to supply -@ for all their .dtso files: $ git grep -- "-@" arch/arm64/ Kind regards, Niklas
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile index f906a868b71a..d827432d5111 100644 --- a/arch/arm64/boot/dts/rockchip/Makefile +++ b/arch/arm64/boot/dts/rockchip/Makefile @@ -117,6 +117,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-nanopc-t6.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-orangepi-5-plus.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-quartzpro64.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-ep.dtbo +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b-pcie-srns.dtbo dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-tiger-haikou.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-toybrick-x0.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-turing-rk1.dtb @@ -127,3 +129,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb + +# Enable support for device-tree overlays +DTC_FLAGS_rk3588-rock-5b += -@ diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso new file mode 100644 index 000000000000..672d748fcc67 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * DT-overlay to run the PCIe3_4L Dual Mode controller in Endpoint mode + * in the SRNS (Separate Reference Clock No Spread) configuration. + * + * NOTE: If using a setup with two ROCK 5B:s, with one board running in + * RC mode and the other board running in EP mode, see also the device + * tree overlay: rk3588-rock-5b-pcie-srns.dtso. + */ + +/dts-v1/; +/plugin/; + +&pcie30phy { + rockchip,rx-common-refclk-mode = <0 0 0 0>; +}; + +&pcie3x4 { + status = "disabled"; +}; + +&pcie3x4_ep { + vpcie3v3-supply = <&vcc3v3_pcie30>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso new file mode 100644 index 000000000000..1a0f1af65c43 --- /dev/null +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b-pcie-srns.dtso @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * DT-overlay to run the PCIe3_4L Dual Mode controller in Root Complex + * mode in the SRNS (Separate Reference Clock No Spread) configuration. + * + * This device tree overlay is only needed (on the RC side) when running + * a setup with two ROCK 5B:s, with one board running in RC mode and the + * other board running in EP mode. + */ + +/dts-v1/; +/plugin/; + +&pcie30phy { + rockchip,rx-common-refclk-mode = <0 0 0 0>; +};
Add rock5b overlays for PCIe endpoint mode support. If using the rock5b as an endpoint against a normal PC, only the rk3588-rock-5b-pcie-ep.dtbo needs to be applied. If using two rock5b:s, with one board as EP and the other board as RC, rk3588-rock-5b-pcie-ep.dtbo and rk3588-rock-5b-pcie-srns.dtbo has to be applied to the respective boards. Signed-off-by: Niklas Cassel <cassel@kernel.org> --- arch/arm64/boot/dts/rockchip/Makefile | 5 +++++ .../boot/dts/rockchip/rk3588-rock-5b-pcie-ep.dtso | 25 ++++++++++++++++++++++ .../dts/rockchip/rk3588-rock-5b-pcie-srns.dtso | 16 ++++++++++++++ 3 files changed, 46 insertions(+)