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Sun, 18 Feb 2024 10:17:47 +0000 Received: from SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn ([fe80::5a5a:fa59:15fd:63dc]) by SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn ([fe80::5a5a:fa59:15fd:63dc%3]) with mapi id 15.20.7249.051; Sun, 18 Feb 2024 10:17:47 +0000 From: Minda Chen To: Conor Dooley , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Lorenzo Pieralisi , Daire McNamara , Emil Renner Berthing , Krzysztof Kozlowski Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-pci@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Mason Huo , Leyfoon Tan , Kevin Xie , Minda Chen Subject: [PATCH v15 12/23] PCI: microchip: Add request_event_irq() callback function Date: Sun, 18 Feb 2024 18:17:31 +0800 Message-Id: <20240218101732.113397-11-minda.chen@starfivetech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20240218101732.113397-1-minda.chen@starfivetech.com> References: <20240218101732.113397-1-minda.chen@starfivetech.com> X-ClientProxiedBy: SHXPR01CA0022.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:1b::31) To SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:25::15) Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SHXPR01MB0863:EE_|SHXPR01MB0765:EE_ X-MS-Office365-Filtering-Correlation-Id: f893e8e6-f9fa-4c3e-919d-08dc306ada62 X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: EVHreCZGcovroKnqowry16R7yUT3pmiYyxNoFuwmWb018uyYTa+VlB9uhQjPbi48NnpYixLhyUFZkwwAqAVaLWyQNXDuHRbqWYOlFZU6j2Uh3yQETDNtschdHcKJKYKS4VjXF0a0/LIx6Cz8goM7shcQ6IPaCU2Ijsz1CmLLvu7rARCEY1uvN2a4P78JVkaFQcdxzt2up/1TcaKpZU28uyQhTwMw5QJbBsNIkp95+YM9+Beh491T+rYkbBTdCyoTD0FxW4Y5JecwRklftm1ulvTj4OMCVaMqOOkOk6NqdPFuLUi5FzT1uPquRmfMdeM4HBjusbPnyXsehyc7u3GRY7Iksn3aTg5Ut7Ic0uPSicoBhKmAgi+5tyC275/gNXljgNd6PHqB52QvSEzvN1mH23FM3WhJsvn7RL6+WOyF67dTLZHm0Bb3il29dVJOepDzDlkPSK12C0KO/cJ+CScZBo3nkwcum72sM1+Mrqybm2Wbtut1nZYAAAPXlbsJDdCjjtHpwjd5PGAn87R7CmcSPZRVD3l5JTTnEo8aES35DQRj6t6qlzv0nK6m36kGlRfoOSiUiC6Ul0ZPxPC49Ksejyde5omm6J5t+peuO11bGmpy/X4jSxu4KwjNcigHtbXFeLsZ/f3/85Vx2Ddd+eqWsWefQYqnni8zNkBeik2h34clNpuA4VdXvz2UsvyO4T8aSozeIUZ2nLsLU7Ck0bTwhahRxxA/8OqpQChISNi2UmjogMXyCNjklcRWLRNf9IWZZ59ypvSyq3hAq7wPMylqsZY/RWQr4VBdx2Nph8NUCCb6TLup2LwALOnVdFHhy8Rj61yOR8Mmd1XtpmSsUOoOXwZYVAmGGT/QBuLtFvf49ThswlUHqcxFS19er9/DPmJ0M4lgBWV9FIqYw97OeikLBPNiNWdYs7+kRm9pQD2Yv6dfRVclxGnWZF8Zb6VwKNKCWTMIVq76dWWu1P4wEa6yyeaFc06Be+65ZxNKx/eZaiL7jRGfk1ExGdtmxtIH8gODaoxIy1rL6hq86YoS1QIIqBY/RhFNBjUzWtt/KrcgpooQPzKNpNM9h6igy8fso0GhEwVFF9/H5wQx2nur/ChT8gmhQsmu7K6/bxD3pFmdaMgoCxlnEzvwgzN/vInBY2BfUsIn6fb53umtKgNPBDdh3PQvAb+Ucy/u4oVHAJwWUbz7hCsk93wuM+utaX7vzkNzZtPPHEWJM2sSyPgZvRx5Etdkr11rxD/EVS8Yvcvv19R4qNr/yHy/FtXYXxUc0KflNFw100v64EGsxSkn1es5iUjHR+aFq1sZI2M4HtvioLTOFPlN3ET1U++2o/tXkiWaaVxrvVyyQ61kRbG/NFChWQ2T+ZOhm20Mli7kDWTN5ecbMWN5A3zXIQXTfsZCyOYsN9CXK17jPi+Fer/6KRErcgmS3nbM2thcj3rdLpboPZcH/lksxg2Chgs/3/u9Ifr+f1zWi8pXwWGi4GH+MetIZ6lb8V3a+pWyzTntxnCX9huq86YtW2tYzh1vLLdwINlFMbGfCAPeYe/GQYaqP82fn1i16oE8QUQZ3Uuq9Y8xXvYwspW/KkmaqgVeVhUKHZI/exNEij+G9+R6AtYrzrPdOg== X-OriginatorOrg: starfivetech.com X-MS-Exchange-CrossTenant-Network-Message-Id: f893e8e6-f9fa-4c3e-919d-08dc306ada62 X-MS-Exchange-CrossTenant-AuthSource: SHXPR01MB0863.CHNPR01.prod.partner.outlook.cn X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Feb 2024 10:17:46.9723 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 06fe3fa3-1221-43d3-861b-5a4ee687a85c X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: zkm6DRXfVFLxJ2iKWdxQUArjQe0ufdlo+XXUA19kLmwq/CyjbbUouqL9cqjthOmAG6oAO4Y0h+ARuqhrpuTnKhUblqpIHTGapxADBHAdSRY= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SHXPR01MB0765 As PLDA dts binding doc(Documentation/devicetree/bindings/pci/ plda,xpressrich3-axi-common.yaml) showed, PLDA PCIe contains an interrupt controller. Microchip Polarfire PCIe add some PCIe interrupts base on PLDA IP interrupt controller. Microchip Polarfire PCIe additional intrerrupts: EVENT_PCIE_L2_EXIT EVENT_PCIE_HOTRST_EXIT EVENT_PCIE_DLUP_EXIT EVENT_SEC_TX_RAM_SEC_ERR EVENT_SEC_RX_RAM_SEC_ERR .... Both codes of request interrupts and mc_event_handler() contain additional interrupts symbol names, these can not be re-used. So add a new plda_event_handler() functions, which implements PLDA interrupt defalt handler, add request_event_irq() callback function to compat Microchip Polorfire PCIe additional interrupts. Signed-off-by: Minda Chen Acked-by: Conor Dooley --- .../pci/controller/plda/pcie-microchip-host.c | 31 ++++++++++++++++--- drivers/pci/controller/plda/pcie-plda.h | 5 +++ 2 files changed, 32 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/plda/pcie-microchip-host.c b/drivers/pci/controller/plda/pcie-microchip-host.c index 0a5cd8b214cd..bf5ce33ee275 100644 --- a/drivers/pci/controller/plda/pcie-microchip-host.c +++ b/drivers/pci/controller/plda/pcie-microchip-host.c @@ -642,6 +642,11 @@ static irqreturn_t mc_event_handler(int irq, void *dev_id) return IRQ_HANDLED; } +static irqreturn_t plda_event_handler(int irq, void *dev_id) +{ + return IRQ_HANDLED; +} + static void plda_handle_event(struct irq_desc *desc) { struct plda_pcie_rp *port = irq_desc_get_handler_data(desc); @@ -803,6 +808,17 @@ static int mc_pcie_init_clks(struct device *dev) return 0; } +static int mc_request_event_irq(struct plda_pcie_rp *plda, int event_irq, + int event) +{ + return devm_request_irq(plda->dev, event_irq, mc_event_handler, + 0, event_cause[event].sym, plda); +} + +static const struct plda_event mc_event = { + .request_event_irq = mc_request_event_irq, +}; + static int plda_pcie_init_irq_domains(struct plda_pcie_rp *port) { struct device *dev = port->dev; @@ -904,7 +920,9 @@ static void mc_disable_interrupts(struct mc_pcie *port) writel_relaxed(GENMASK(31, 0), bridge_base_addr + ISTATUS_HOST); } -static int plda_init_interrupts(struct platform_device *pdev, struct plda_pcie_rp *port) +static int plda_init_interrupts(struct platform_device *pdev, + struct plda_pcie_rp *port, + const struct plda_event *event) { struct device *dev = &pdev->dev; int irq; @@ -928,8 +946,13 @@ static int plda_init_interrupts(struct platform_device *pdev, struct plda_pcie_r return -ENXIO; } - ret = devm_request_irq(dev, event_irq, mc_event_handler, - 0, event_cause[i].sym, port); + if (event->request_event_irq) + ret = event->request_event_irq(port, event_irq, i); + else + ret = devm_request_irq(dev, event_irq, + plda_event_handler, + 0, NULL, port); + if (ret) { dev_err(dev, "failed to request IRQ %d\n", event_irq); return ret; @@ -983,7 +1006,7 @@ static int mc_platform_init(struct pci_config_window *cfg) return ret; /* Address translation is up; safe to enable interrupts */ - ret = plda_init_interrupts(pdev, &port->plda); + ret = plda_init_interrupts(pdev, &port->plda, &mc_event); if (ret) return ret; diff --git a/drivers/pci/controller/plda/pcie-plda.h b/drivers/pci/controller/plda/pcie-plda.h index f7e900b395f8..935686bba837 100644 --- a/drivers/pci/controller/plda/pcie-plda.h +++ b/drivers/pci/controller/plda/pcie-plda.h @@ -127,6 +127,11 @@ struct plda_pcie_rp { int num_events; }; +struct plda_event { + int (*request_event_irq)(struct plda_pcie_rp *pcie, + int event_irq, int event); +}; + void plda_pcie_setup_window(void __iomem *bridge_base_addr, u32 index, phys_addr_t axi_addr, phys_addr_t pci_addr, size_t size);