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[v2] PCI: Increase maximum PCIe physical function number to 7 for non-ARI devices

Message ID 20240216190113.20341-1-beanhuo@iokpp.de
State New
Headers show
Series [v2] PCI: Increase maximum PCIe physical function number to 7 for non-ARI devices | expand

Commit Message

Bean Huo Feb. 16, 2024, 7:01 p.m. UTC 
From: Bean Huo <beanhuo@micron.com>

The PCIe specification allows up to 8 Physical Functions (PFs) per endpoint
when ARI (Alternative Routing-ID Interpretation) is not supported. Previously,
our implementation erroneously limited the maximum number of PFs to 7 for
endpoints without ARI support.

This patch corrects the maximum PF count to adhere to the PCIe specification
by allowing up to 8 PFs on non-ARI endpoints. This change ensures better
compliance with the standard and improves compatibility with devices relying
on this specification.

The necessity for this adjustment was verified by a thorough review of the
"Alternative Routing-ID Interpretation (ARI)" section in the PCIe 3.0 Spec,
which first introduced ARI.

Fixes: c3df83e01a96 ("PCI: Clean up pci_scan_slot()")
Cc: stable@vger.kernel.org
Signed-off-by: Bean Huo <beanhuo@micron.com>
---
Changelog:
	v1--v2:
		1. Add Fixes tag
		2. Modify commit message
---
 drivers/pci/probe.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

Comments

Kuppuswamy Sathyanarayanan Feb. 16, 2024, 10:26 p.m. UTC | #1 
On 2/16/24 11:01 AM, Bean Huo wrote:
> From: Bean Huo <beanhuo@micron.com>
>
> The PCIe specification allows up to 8 Physical Functions (PFs) per endpoint
> when ARI (Alternative Routing-ID Interpretation) is not supported. Previously,
> our implementation erroneously limited the maximum number of PFs to 7 for
> endpoints without ARI support.
I would quote specification reference here, like below:

As per PCIe specification r6.2, sec titled "Alternative Routing-ID Interpretation
(ARI)", up to 8 [fn # 0..7] functions are allowed in an non ARI capable device.

It looks like for an ARI capable device the limit is 256. Why not add that
check as well?

>
> This patch corrects the maximum PF count to adhere to the PCIe specification
> by allowing up to 8 PFs on non-ARI endpoints. This change ensures better
> compliance with the standard and improves compatibility with devices relying
> on this specification.
>
> The necessity for this adjustment was verified by a thorough review of the
> "Alternative Routing-ID Interpretation (ARI)" section in the PCIe 3.0 Spec,
> which first introduced ARI.

I would always use latest PCIe spec for reference.

>
> Fixes: c3df83e01a96 ("PCI: Clean up pci_scan_slot()")
> Cc: stable@vger.kernel.org
> Signed-off-by: Bean Huo <beanhuo@micron.com>
> ---
> Changelog:
> 	v1--v2:
> 		1. Add Fixes tag
> 		2. Modify commit message
> ---
>  drivers/pci/probe.c | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index ed6b7f48736a..8c3d0f63bc13 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -2630,7 +2630,8 @@ static int next_fn(struct pci_bus *bus, struct pci_dev *dev, int fn)
>  	if (pci_ari_enabled(bus))
>  		return next_ari_fn(bus, dev, fn);
>  
> -	if (fn >= 7)
> +	/* If EP does not support ARI, the maximum number of functions should be 7 */
> +	if (fn > 7)
>  		return -ENODEV;
>  	/* only multifunction devices may have more functions */
>  	if (dev && !dev->multifunction)
Bjorn Helgaas Feb. 16, 2024, 10:41 p.m. UTC | #2 
On Fri, Feb 16, 2024 at 02:26:47PM -0800, Kuppuswamy Sathyanarayanan wrote:
> 
> On 2/16/24 11:01 AM, Bean Huo wrote:
> > From: Bean Huo <beanhuo@micron.com>
> >
> > The PCIe specification allows up to 8 Physical Functions (PFs) per endpoint
> > when ARI (Alternative Routing-ID Interpretation) is not supported. Previously,
> > our implementation erroneously limited the maximum number of PFs to 7 for
> > endpoints without ARI support.
> I would quote specification reference here, like below:
> 
> As per PCIe specification r6.2, sec titled "Alternative Routing-ID
> Interpretation (ARI)", up to 8 [fn # 0..7] functions are allowed in
> an non ARI capable device.

That's fine, just know that I silently convert citations like that
to "PCIe r6.2, sec 6.13" because I don't like having to grep for the
text ;)

Bjorn
Bean Huo Feb. 19, 2024, 10:50 a.m. UTC | #3 
On Fri, 2024-02-16 at 14:26 -0800, Kuppuswamy Sathyanarayanan wrote:
> It looks like for an ARI capable device the limit is 256. Why not add
> that
> check as well?

" With ARI, the 16-bit field is interpreted as two fields
instead of three: an 8-bit Bus Number and an 8-bit Function Number -
the Device Number field is eliminated. This new
interpretation enables an ARI Device to support up to 256 Functions
[0..255] instead of 8 Functions [0..7]."

the above statement on PCIe Spec highlights that since the Function
Number field in an ARI-enabled device is 8 bits, it inherently supports
numbering from 0 to 255. Thus, there's no need for additional checks to
limit the function number to this range; the 8-bit size of the field
naturally imposes this limit. This efficient use of the available
address space aligns with the goals of ARI to enhance device
functionality within the PCIe specification.

Kind regards,
Bean
diff mbox series

Patch

diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index ed6b7f48736a..8c3d0f63bc13 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -2630,7 +2630,8 @@  static int next_fn(struct pci_bus *bus, struct pci_dev *dev, int fn)
 	if (pci_ari_enabled(bus))
 		return next_ari_fn(bus, dev, fn);
 
-	if (fn >= 7)
+	/* If EP does not support ARI, the maximum number of functions should be 7 */
+	if (fn > 7)
 		return -ENODEV;
 	/* only multifunction devices may have more functions */
 	if (dev && !dev->multifunction)