| Message ID | 20240102-j7200-pcie-s2r-v1-13-84e55da52400@bootlin.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add suspend to ram support for PCIe on J7200 | expand |
On Mon, Jan 15, 2024 at 6:16 PM Thomas Richard <thomas.richard@bootlin.com> wrote: > > From: Théo Lebrun <theo.lebrun@bootlin.com> > > Move reset GPIO to device struct, so it can be used at suspend and > resume stages. ... > - struct gpio_desc *gpiod; You can leave this and make the patch much lighter. ... > if (ret != -EPROBE_DEFER) > dev_err(dev, "Failed to get reset GPIO\n"); Side note (not related to this change): perhaps dev_err_probe()?
On Mon, Jan 15, 2024 at 05:14:54PM +0100, Thomas Richard wrote: > From: Théo Lebrun <theo.lebrun@bootlin.com> > > Move reset GPIO to device struct, so it can be used at suspend and > resume stages. s/Move/Add/ since we're not moving it from one struct to another. (In subject also.) s/device struct/struct j721e_pcie/ since "device struct" could also refer to the "struct device", which is obviously not relevant here. BTW, if you capitalize the PCI subject lines to match previous history, it will save some work when applying this series. Also rewrap commit logs to fill 75 columns and add blank lines between paragraphs (noticed in patch 12/14). > @@ -54,6 +54,7 @@ struct j721e_pcie { > struct clk *refclk; > u32 mode; > u32 num_lanes; > + struct gpio_desc *reset_gpio; > void __iomem *user_cfg_base; > void __iomem *intd_cfg_base; > u32 linkdown_irq_regfield; > @@ -359,7 +360,6 @@ static int j721e_pcie_probe(struct platform_device *pdev) > struct j721e_pcie *pcie; > struct cdns_pcie_rc *rc = NULL; > struct cdns_pcie_ep *ep = NULL; > - struct gpio_desc *gpiod; > void __iomem *base; > struct clk *clk; > u32 num_lanes;
diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c index 9b343a46da11..477275d72257 100644 --- a/drivers/pci/controller/cadence/pci-j721e.c +++ b/drivers/pci/controller/cadence/pci-j721e.c @@ -54,6 +54,7 @@ struct j721e_pcie { struct clk *refclk; u32 mode; u32 num_lanes; + struct gpio_desc *reset_gpio; void __iomem *user_cfg_base; void __iomem *intd_cfg_base; u32 linkdown_irq_regfield; @@ -359,7 +360,6 @@ static int j721e_pcie_probe(struct platform_device *pdev) struct j721e_pcie *pcie; struct cdns_pcie_rc *rc = NULL; struct cdns_pcie_ep *ep = NULL; - struct gpio_desc *gpiod; void __iomem *base; struct clk *clk; u32 num_lanes; @@ -468,9 +468,9 @@ static int j721e_pcie_probe(struct platform_device *pdev) switch (mode) { case PCI_MODE_RC: - gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); - if (IS_ERR(gpiod)) { - ret = PTR_ERR(gpiod); + pcie->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); + if (IS_ERR(pcie->reset_gpio)) { + ret = PTR_ERR(pcie->reset_gpio); if (ret != -EPROBE_DEFER) dev_err(dev, "Failed to get reset GPIO\n"); goto err_get_sync; @@ -504,9 +504,9 @@ static int j721e_pcie_probe(struct platform_device *pdev) * mode is selected while enabling the PHY. So deassert PERST# * after 100 us. */ - if (gpiod) { + if (pcie->reset_gpio) { usleep_range(100, 200); - gpiod_set_value_cansleep(gpiod, 1); + gpiod_set_value_cansleep(pcie->reset_gpio, 1); } ret = cdns_pcie_host_setup(rc, true);