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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by MWH0EPF000989E9.mail.protection.outlook.com (10.167.241.136) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7068.20 via Frontend Transport; Mon, 4 Dec 2023 06:07:01 +0000 Received: from AUS-P9-MLIMONCI.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Mon, 4 Dec 2023 00:06:55 -0600 From: Mario Limonciello To: Bjorn Helgaas CC: "Rafael J . Wysocki" , Hans de Goede , Shyam Sundar S K , "open list:PCI SUBSYSTEM" , "open list:X86 PLATFORM DRIVERS" , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , "Lukas Wunner" , Kai-Heng Feng , , , Mario Limonciello Subject: [PATCH v2 4/4] platform/x86/amd: pmc: Add support for using constraints to decide D3 policy Date: Sat, 2 Dec 2023 22:10:46 -0600 Message-ID: <20231203041046.38655-5-mario.limonciello@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231203041046.38655-1-mario.limonciello@amd.com> References: <20231203041046.38655-1-mario.limonciello@amd.com> Precedence: bulk X-Mailing-List: linux-pci@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MWH0EPF000989E9:EE_|CH2PR12MB4922:EE_ X-MS-Office365-Filtering-Correlation-Id: 73cd6dd2-4037-4cb3-b594-08dbf48f3b84 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 6ZEswAeWATwsMTTgSnDiTHdD5nRnCQNh+Jx/Kb6XII6RJBF2niIuEb+tpViSpjkBlnPD3pSuppxonGigd2+IWVYrgGY18fUpbv9dUwOW5WbK1ha7hdSkX6UjgK48oh2yPqzU5g+02v3Yb8ZFqFtYrD7TevPz+E7vp2Xy5FX0e6MLrsNuW/FsWxwrj//nDPLKiH0OvxQTfCAcno+cb1tW4UXXwGEhU3n0dnNulhQVfd08BXxTbgFUGNFrG/8nf1kbgDILfOuECFPsh/MshnjqH1hCjIoAcigwaeapFlPQejy+Txoe95PYrmjALHCV820lsv32bT+lWEPW1AiTbH53TjKo3uT2+1kEHlZfIwtHuSndrnbm+y7+Bq8DDwlEwsLSvyUHeL4ZikhQYOI3WelhwStADreD74cAOzZKtPl+0HV+VF3fo9B1jWYW5YN7NYFVqil3seVYbCWLGu0FS6pi1xpgxov8TPpgXoBQ4XT8kG2hZrUT9j5862EycF9yur71ovlt1R5GjZcsW+U5Ny/edHTxzO+nETMzs+tCe7qakqfgFSWNCnLWdbcFbvaLT/f+m8sh03etE7mc8r+/fFUxfTcPd2Rdk006Uu1vtS/LD8Uygqp3a2jQMOXCcSCmzI+uAlVRex1MQucCsBSJ+8byGmgutkQov36h9BCypPR9VlhGgnUrcBNRqoCP+qokax9S0T1UbvaV4u3RXkD9OgOQx2EYUbutUc4oeZMNXRM0ugYTsIpc0DgM0R7jrpYM/CQR X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(136003)(396003)(376002)(346002)(230922051799003)(451199024)(186009)(64100799003)(82310400011)(1800799012)(36840700001)(40470700004)(46966006)(70206006)(70586007)(316002)(6916009)(54906003)(6666004)(40460700003)(966005)(478600001)(5660300002)(7416002)(41300700001)(36756003)(2906002)(4326008)(8676002)(8936002)(44832011)(86362001)(83380400001)(2616005)(36860700001)(47076005)(81166007)(356005)(426003)(336012)(26005)(16526019)(82740400003)(1076003)(40480700001)(7696005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Dec 2023 06:07:01.6923 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 73cd6dd2-4037-4cb3-b594-08dbf48f3b84 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MWH0EPF000989E9.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4922 X-Spam-Level: * The default kernel policy will allow modern machines to effectively put all PCIe bridges into PCI D3. This policy doesn't match what Windows uses. In Windows the driver stack includes a "Power Engine Plugin" (uPEP driver) to decide the policy for integrated devices using PEP device constraints. Device constraints are expressed as a number in the _DSM of the PNP0D80 device and exported by the kernel in acpi_get_lps0_constraint(). Add support for SoCs to use constraints on Linux as well for deciding target state for integrated PCI bridges. Disable existing production SoCs by default with this change. Link: https://learn.microsoft.com/en-us/windows-hardware/design/device-experiences/platform-design-for-modern-standby#low-power-core-silicon-cpu-soc-dram Acked-by: Hans de Goede Signed-off-by: Mario Limonciello --- drivers/platform/x86/amd/pmc/pmc.c | 57 ++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/platform/x86/amd/pmc/pmc.c index c3104714b480..9aa6cf4fabf1 100644 --- a/drivers/platform/x86/amd/pmc/pmc.c +++ b/drivers/platform/x86/amd/pmc/pmc.c @@ -793,6 +793,61 @@ static int amd_pmc_czn_wa_irq1(struct amd_pmc_dev *pdev) return 0; } +static inline void amd_pmc_apply_constraint(struct pci_dev *pci_dev, bool apply) +{ + if (apply) + pci_d3cold_disable(pci_dev); + else + pci_d3cold_enable(pci_dev); +} + +/* + * Constraints are specified in the ACPI LPS0 device and specify what the + * platform intended for devices that are internal to the SoC. + * + * If a constraint is present and >= to ACPI_STATE_D3, then enable D3. + * If a constraint is not present or < ACPI_STATE_D3, then disable D3. + */ +static void amd_pmc_check_constraints(struct amd_pmc_dev *pdev, bool apply) +{ + struct pci_dev *pci_dev = NULL; + struct acpi_device *adev; + int constraint; + + switch (pdev->cpu_id) { + case AMD_CPU_ID_RV: + case AMD_CPU_ID_RN: + case AMD_CPU_ID_YC: + case AMD_CPU_ID_CB: + case AMD_CPU_ID_PS: + case AMD_CPU_ID_SP: + return; + default: + break; + } + + while ((pci_dev = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, pci_dev))) { + adev = ACPI_COMPANION(&pci_dev->dev); + if (!adev) + continue; + constraint = acpi_get_lps0_constraint(adev); + dev_dbg(&pci_dev->dev, "constraint is %d\n", constraint); + + switch (constraint) { + case ACPI_STATE_UNKNOWN: + case ACPI_STATE_D0: + case ACPI_STATE_D1: + case ACPI_STATE_D2: + amd_pmc_apply_constraint(pci_dev, apply); + continue; + /* use the logic pci_bridge_d3_possible() to decide */ + case ACPI_STATE_D3: + default: + continue; + } + } +} + static int amd_pmc_verify_czn_rtc(struct amd_pmc_dev *pdev, u32 *arg) { struct rtc_device *rtc_device; @@ -1099,6 +1154,7 @@ static int amd_pmc_probe(struct platform_device *pdev) amd_pmc_quirks_init(dev); } + amd_pmc_check_constraints(dev, TRUE); amd_pmc_dbgfs_register(dev); pm_report_max_hw_sleep(U64_MAX); return 0; @@ -1114,6 +1170,7 @@ static void amd_pmc_remove(struct platform_device *pdev) if (IS_ENABLED(CONFIG_SUSPEND)) acpi_unregister_lps0_dev(&amd_pmc_s2idle_dev_ops); + amd_pmc_check_constraints(dev, FALSE); amd_pmc_dbgfs_unregister(dev); pci_dev_put(dev->rdev); mutex_destroy(&dev->lock);