| Message ID | 20231201115028.84351-1-jiaxun.yang@flygoat.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v6] pci: loongson: Workaround MIPS firmware MRRS settings | expand |
Acked-by: Huacai Chen <chenhuacai@loongson.cn> On Fri, Dec 1, 2023 at 7:50 PM Jiaxun Yang <jiaxun.yang@flygoat.com> wrote: > > This is a partial revert of commit 8b3517f88ff2 ("PCI: > loongson: Prevent LS7A MRRS increases") for MIPS based Loongson. > > There are many MIPS based Loongson systems in wild that > shipped with firmware which does not set maximum MRRS properly. > > Limiting MRRS to 256 for all as MIPS Loongson comes with higher > MRRS support is considered rare. > > It must be done at device enablement stage because MRRS setting > may get lost if the parent bridge lost PCI_COMMAND_MASTER, and > we are only sure parent bridge is enabled at this point. > > Cc: stable@vger.kernel.org > Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217680 > Fixes: 8b3517f88ff2 ("PCI: loongson: Prevent LS7A MRRS increases") > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> > --- > v4: Improve commit message > v5: > - Improve commit message and comments. > - Style fix from Huacai's off-list input. > v6: Fix a typo > --- > drivers/pci/controller/pci-loongson.c | 47 ++++++++++++++++++++++++--- > 1 file changed, 42 insertions(+), 5 deletions(-) > > diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c > index d45e7b8dc530..e181d99decf1 100644 > --- a/drivers/pci/controller/pci-loongson.c > +++ b/drivers/pci/controller/pci-loongson.c > @@ -80,13 +80,50 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > DEV_LS7A_LPC, system_bus_quirk); > > +/* > + * Some Loongson PCIe ports have h/w limitations of maximum read > + * request size. They can't handle anything larger than this. > + * Sane firmware will set proper MRRS at boot, so we only need > + * no_inc_mrrs for bridges. However, some MIPS Loongson firmware > + * won't set MRRS properly, and we have to enforce maximum safe > + * MRRS, which is 256 bytes. > + */ > +#ifdef CONFIG_MIPS > +static void loongson_set_min_mrrs_quirk(struct pci_dev *pdev) > +{ > + struct pci_bus *bus = pdev->bus; > + struct pci_dev *bridge; > + static const struct pci_device_id bridge_devids[] = { > + { PCI_VDEVICE(LOONGSON, DEV_LS2K_PCIE_PORT0) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT0) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT1) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT2) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT3) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT4) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT5) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT6) }, > + { 0, }, > + }; > + > + /* look for the matching bridge */ > + while (!pci_is_root_bus(bus)) { > + bridge = bus->self; > + bus = bus->parent; > + > + if (pci_match_id(bridge_devids, bridge)) { > + if (pcie_get_readrq(pdev) > 256) { > + pci_info(pdev, "limiting MRRS to 256\n"); > + pcie_set_readrq(pdev, 256); > + } > + break; > + } > + } > +} > +DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_set_min_mrrs_quirk); > +#endif > + > static void loongson_mrrs_quirk(struct pci_dev *pdev) > { > - /* > - * Some Loongson PCIe ports have h/w limitations of maximum read > - * request size. They can't handle anything larger than this. So > - * force this limit on any devices attached under these ports. > - */ > struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); > > bridge->no_inc_mrrs = 1; > -- > 2.34.1 >
On Fri, Dec 01, 2023 at 11:50:28AM +0000, Jiaxun Yang wrote: > This is a partial revert of commit 8b3517f88ff2 ("PCI: > loongson: Prevent LS7A MRRS increases") for MIPS based Loongson. > > There are many MIPS based Loongson systems in wild that > shipped with firmware which does not set maximum MRRS properly. > > Limiting MRRS to 256 for all as MIPS Loongson comes with higher > MRRS support is considered rare. > > It must be done at device enablement stage because MRRS setting > may get lost if the parent bridge lost PCI_COMMAND_MASTER, and > we are only sure parent bridge is enabled at this point. > > Cc: stable@vger.kernel.org > Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217680 > Fixes: 8b3517f88ff2 ("PCI: loongson: Prevent LS7A MRRS increases") > Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Applied to for-linus for v6.7, thanks! > --- > v4: Improve commit message > v5: > - Improve commit message and comments. > - Style fix from Huacai's off-list input. > v6: Fix a typo > --- > drivers/pci/controller/pci-loongson.c | 47 ++++++++++++++++++++++++--- > 1 file changed, 42 insertions(+), 5 deletions(-) > > diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c > index d45e7b8dc530..e181d99decf1 100644 > --- a/drivers/pci/controller/pci-loongson.c > +++ b/drivers/pci/controller/pci-loongson.c > @@ -80,13 +80,50 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, > DEV_LS7A_LPC, system_bus_quirk); > > +/* > + * Some Loongson PCIe ports have h/w limitations of maximum read > + * request size. They can't handle anything larger than this. > + * Sane firmware will set proper MRRS at boot, so we only need > + * no_inc_mrrs for bridges. However, some MIPS Loongson firmware > + * won't set MRRS properly, and we have to enforce maximum safe > + * MRRS, which is 256 bytes. > + */ > +#ifdef CONFIG_MIPS > +static void loongson_set_min_mrrs_quirk(struct pci_dev *pdev) > +{ > + struct pci_bus *bus = pdev->bus; > + struct pci_dev *bridge; > + static const struct pci_device_id bridge_devids[] = { > + { PCI_VDEVICE(LOONGSON, DEV_LS2K_PCIE_PORT0) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT0) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT1) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT2) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT3) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT4) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT5) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT6) }, > + { 0, }, > + }; > + > + /* look for the matching bridge */ > + while (!pci_is_root_bus(bus)) { > + bridge = bus->self; > + bus = bus->parent; > + > + if (pci_match_id(bridge_devids, bridge)) { > + if (pcie_get_readrq(pdev) > 256) { > + pci_info(pdev, "limiting MRRS to 256\n"); > + pcie_set_readrq(pdev, 256); > + } > + break; > + } > + } > +} > +DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_set_min_mrrs_quirk); > +#endif > + > static void loongson_mrrs_quirk(struct pci_dev *pdev) > { > - /* > - * Some Loongson PCIe ports have h/w limitations of maximum read > - * request size. They can't handle anything larger than this. So > - * force this limit on any devices attached under these ports. > - */ > struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); > > bridge->no_inc_mrrs = 1; > -- > 2.34.1 >
On Fri, Dec 01, 2023 at 11:50:28AM +0000, Jiaxun Yang wrote: > ... > + { PCI_VDEVICE(LOONGSON, DEV_LS2K_PCIE_PORT0) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT0) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT1) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT2) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT3) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT4) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT5) }, > + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT6) }, P.S. I notice most of these Device IDs are not in the lspci database at https://admin.pci-ids.ucw.cz/read/PC/0014. It's easy to add them; there's a link at the bottom of that page. Some, e.g., 0x7a09 (DEV_LS7A_PCIE_PORT0), are described as "PCI-to-PCI Bridge". I had the impression these were Root Ports. If so, the description could be more specific. Bjorn
diff --git a/drivers/pci/controller/pci-loongson.c b/drivers/pci/controller/pci-loongson.c index d45e7b8dc530..e181d99decf1 100644 --- a/drivers/pci/controller/pci-loongson.c +++ b/drivers/pci/controller/pci-loongson.c @@ -80,13 +80,50 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_LOONGSON, DEV_LS7A_LPC, system_bus_quirk); +/* + * Some Loongson PCIe ports have h/w limitations of maximum read + * request size. They can't handle anything larger than this. + * Sane firmware will set proper MRRS at boot, so we only need + * no_inc_mrrs for bridges. However, some MIPS Loongson firmware + * won't set MRRS properly, and we have to enforce maximum safe + * MRRS, which is 256 bytes. + */ +#ifdef CONFIG_MIPS +static void loongson_set_min_mrrs_quirk(struct pci_dev *pdev) +{ + struct pci_bus *bus = pdev->bus; + struct pci_dev *bridge; + static const struct pci_device_id bridge_devids[] = { + { PCI_VDEVICE(LOONGSON, DEV_LS2K_PCIE_PORT0) }, + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT0) }, + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT1) }, + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT2) }, + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT3) }, + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT4) }, + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT5) }, + { PCI_VDEVICE(LOONGSON, DEV_LS7A_PCIE_PORT6) }, + { 0, }, + }; + + /* look for the matching bridge */ + while (!pci_is_root_bus(bus)) { + bridge = bus->self; + bus = bus->parent; + + if (pci_match_id(bridge_devids, bridge)) { + if (pcie_get_readrq(pdev) > 256) { + pci_info(pdev, "limiting MRRS to 256\n"); + pcie_set_readrq(pdev, 256); + } + break; + } + } +} +DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, loongson_set_min_mrrs_quirk); +#endif + static void loongson_mrrs_quirk(struct pci_dev *pdev) { - /* - * Some Loongson PCIe ports have h/w limitations of maximum read - * request size. They can't handle anything larger than this. So - * force this limit on any devices attached under these ports. - */ struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); bridge->no_inc_mrrs = 1;
This is a partial revert of commit 8b3517f88ff2 ("PCI: loongson: Prevent LS7A MRRS increases") for MIPS based Loongson. There are many MIPS based Loongson systems in wild that shipped with firmware which does not set maximum MRRS properly. Limiting MRRS to 256 for all as MIPS Loongson comes with higher MRRS support is considered rare. It must be done at device enablement stage because MRRS setting may get lost if the parent bridge lost PCI_COMMAND_MASTER, and we are only sure parent bridge is enabled at this point. Cc: stable@vger.kernel.org Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217680 Fixes: 8b3517f88ff2 ("PCI: loongson: Prevent LS7A MRRS increases") Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> --- v4: Improve commit message v5: - Improve commit message and comments. - Style fix from Huacai's off-list input. v6: Fix a typo --- drivers/pci/controller/pci-loongson.c | 47 ++++++++++++++++++++++++--- 1 file changed, 42 insertions(+), 5 deletions(-)