| Message ID | 20231010204436.1000644-5-helgaas@kernel.org |
|---|---|
| State | New |
| Headers | show |
| Series | PCI: Use FIELD_GET() and FIELD_PREP() | expand |
On Tue, 10 Oct 2023 15:44:30 -0500 Bjorn Helgaas <helgaas@kernel.org> wrote: > From: Bjorn Helgaas <bhelgaas@google.com> > > The PASID Capability and Control registers are both 16 bits wide. Use > 16-bit wide constants in field names to match the register width. No > functional change intended. > > Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> > --- > include/uapi/linux/pci_regs.h | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index 34bf037993f3..6af1f8d53e97 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -930,12 +930,12 @@ > > /* Process Address Space ID */ > #define PCI_PASID_CAP 0x04 /* PASID feature register */ > -#define PCI_PASID_CAP_EXEC 0x02 /* Exec permissions Supported */ > -#define PCI_PASID_CAP_PRIV 0x04 /* Privilege Mode Supported */ > +#define PCI_PASID_CAP_EXEC 0x0002 /* Exec permissions Supported */ > +#define PCI_PASID_CAP_PRIV 0x0004 /* Privilege Mode Supported */ > #define PCI_PASID_CTRL 0x06 /* PASID control register */ > -#define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */ > -#define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */ > -#define PCI_PASID_CTRL_PRIV 0x04 /* Privilege Mode Enable */ > +#define PCI_PASID_CTRL_ENABLE 0x0001 /* Enable bit */ > +#define PCI_PASID_CTRL_EXEC 0x0002 /* Exec permissions Enable */ > +#define PCI_PASID_CTRL_PRIV 0x0004 /* Privilege Mode Enable */ > #define PCI_EXT_CAP_PASID_SIZEOF 8 > > /* Single Root I/O Virtualization */
On Tue, 10 Oct 2023, Bjorn Helgaas wrote: > From: Bjorn Helgaas <bhelgaas@google.com> > > The PASID Capability and Control registers are both 16 bits wide. Use > 16-bit wide constants in field names to match the register width. No > functional change intended. > > Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> > --- > include/uapi/linux/pci_regs.h | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index 34bf037993f3..6af1f8d53e97 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -930,12 +930,12 @@ > > /* Process Address Space ID */ > #define PCI_PASID_CAP 0x04 /* PASID feature register */ > -#define PCI_PASID_CAP_EXEC 0x02 /* Exec permissions Supported */ > -#define PCI_PASID_CAP_PRIV 0x04 /* Privilege Mode Supported */ > +#define PCI_PASID_CAP_EXEC 0x0002 /* Exec permissions Supported */ > +#define PCI_PASID_CAP_PRIV 0x0004 /* Privilege Mode Supported */ > #define PCI_PASID_CTRL 0x06 /* PASID control register */ > -#define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */ > -#define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */ > -#define PCI_PASID_CTRL_PRIV 0x04 /* Privilege Mode Enable */ > +#define PCI_PASID_CTRL_ENABLE 0x0001 /* Enable bit */ > +#define PCI_PASID_CTRL_EXEC 0x0002 /* Exec permissions Enable */ > +#define PCI_PASID_CTRL_PRIV 0x0004 /* Privilege Mode Enable */ > #define PCI_EXT_CAP_PASID_SIZEOF 8 Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 34bf037993f3..6af1f8d53e97 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -930,12 +930,12 @@ /* Process Address Space ID */ #define PCI_PASID_CAP 0x04 /* PASID feature register */ -#define PCI_PASID_CAP_EXEC 0x02 /* Exec permissions Supported */ -#define PCI_PASID_CAP_PRIV 0x04 /* Privilege Mode Supported */ +#define PCI_PASID_CAP_EXEC 0x0002 /* Exec permissions Supported */ +#define PCI_PASID_CAP_PRIV 0x0004 /* Privilege Mode Supported */ #define PCI_PASID_CTRL 0x06 /* PASID control register */ -#define PCI_PASID_CTRL_ENABLE 0x01 /* Enable bit */ -#define PCI_PASID_CTRL_EXEC 0x02 /* Exec permissions Enable */ -#define PCI_PASID_CTRL_PRIV 0x04 /* Privilege Mode Enable */ +#define PCI_PASID_CTRL_ENABLE 0x0001 /* Enable bit */ +#define PCI_PASID_CTRL_EXEC 0x0002 /* Exec permissions Enable */ +#define PCI_PASID_CTRL_PRIV 0x0004 /* Privilege Mode Enable */ #define PCI_EXT_CAP_PASID_SIZEOF 8 /* Single Root I/O Virtualization */