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Received: from AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) by DB8PR04MB7161.eurprd04.prod.outlook.com (2603:10a6:10:124::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6652.28; Wed, 9 Aug 2023 15:36:14 +0000 Received: from AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::d0d5:3604:98da:20b1]) by AM6PR04MB4838.eurprd04.prod.outlook.com ([fe80::d0d5:3604:98da:20b1%7]) with mapi id 15.20.6652.028; Wed, 9 Aug 2023 15:36:14 +0000 From: Frank Li To: helgaas@kernel.org Cc: Frank.li@nxp.com, bhelgaas@google.com, devicetree@vger.kernel.org, gustavo.pimentel@synopsys.com, imx@lists.linux.dev, kw@linux.com, leoyang.li@nxp.com, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lorenzo.pieralisi@arm.com, lpieralisi@kernel.org, mani@kernel.org, manivannan.sadhasivam@linaro.org, minghuan.lian@nxp.com, mingkai.hu@nxp.com, robh+dt@kernel.org, roy.zang@nxp.com, shawnguo@kernel.org, zhiqiang.hou@nxp.com Subject: [PATCH v11 2/3] PCI: dwc: Implement general suspend/resume functionality for L2/L3 transitions Date: Wed, 9 Aug 2023 11:35:39 -0400 Message-Id: <20230809153540.834653-3-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230809153540.834653-1-Frank.Li@nxp.com> References: <20230809153540.834653-1-Frank.Li@nxp.com> X-ClientProxiedBy: BY5PR04CA0018.namprd04.prod.outlook.com (2603:10b6:a03:1d0::28) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|DB8PR04MB7161:EE_ X-MS-Office365-Filtering-Correlation-Id: a4c57f22-0cc6-4ce8-875c-08db98ee5d6f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: FjX/6lupl9AgMqntJ4fCyeuT8SF2O03fMeQ8ghfR1X0Plk/EicvbAdvbOYIrAHgHuN6M8X3kyKJFvQ6N099R+xf9hF+q7ReVcQS9bSE8v8VeHM/AG6qvn7Ydt30AA8wuyVc1DyszbPz9w8mVLtfmkRjnCORMnwnznUNFDhm9i0dCBcftFFDP98jWd27EqRq17WbVge7URvTG685Nk/IOZXOi0u+QaeqTxlW/SOKBbNBRIMU8aOfBjOFQbcl/pxDj6U3ZYiqlUqj+r0n5rV1OsFp0B0Dvhuia1nYD+EYLTi+XqCLRXc2YdIlhWf9r03OB5DmvZW4vRsoJxCXjMei0AQ/Aj5pV2CrSt15eQhbuUtw7y4RkJf2pvmItnZgUaRHH7N1/DRH3f9UnvEedRzN4mMFzLQyDlFTNNUyULubVVLC4xYvRFy5v7t+nVRf4Mo7Icl5aIUp4d3/d0jQ9ftn91bTpVEABR337ImB9OR3QpuivPSw8ih4IlHH9frC1pjOlPX3BeI/FDEvIJ7eRyFj5OiC/i4C2NKXpHWDI0EjhXnTErP0fxv4fRuQ88oomlPKDRm63TqXd8xCwZl2ZCxFBTOqf/RbZqMgF6cH+XBoFQ9Mbu7R7AHSKq/Hl+CnnulM+gwgzmq2uzy7Lqswp/Kf8NbLXypOvXwliRuUPXEb5jioGSYlaDmP9UryxHAZmRSbQOEQDgASgdL8ikfKnij5lwbxlhjxjhIHWfEsjXZ5PgF23XRFz9TZdpUAO6qDGaMPP/n7rbjgcSHxuzXSiW7zFE3TnMYCF7R56rFwQbC3GdrwsmauXuUJlgYZb3udbrAmLLrghehNGexMUS7XlUXvZ/8b3Lrw0fQmFK8hCg1EFhVVkUr1H8PeUGhGXXPyRSBei37rEg9JTiPJrbcDA7a0mnuNAAgWgh5mBt2w/7C+Pn9MZb96CFheQ7PVGrP894k5PetlM08i+9zqz+GlFGaFfbQaTI8uUcFU/raIiKq302ev1sW+t7WOXMdqGDpmaBpfEjRWS3l66VNFpfuXbFu4zs5osxkuAh5PPpgN8MQ0M5M55jXli8t+dhg55HoN6we+fa0+C+dtduAm273vzt8e9hpwa5hj9pThxfmey+OJsJsSS+7ENOtSNUC5YyoN1AAjgBNMBBjd+ye8zu7Rh3tHUxt5iM0NqQZ6ClKfb2tG0CCy6udiIBc43qfa4L46oqRrsCqTz+u61vUBZG6DiDmP9Yv70+5T9f7G5B67Ww/kVFyDrVFHyGmowlQJSTcxMWIkQFLc4XiyCYE2Gm9B52UatuNJxJwi4hn3+UDlcVr84JxlDY/pfEqPMn3Q/pBGWVIA/fxs7slZAQfn7xGZVOjp0eKKsFHjb43SuMeKfapSYHD4y6rPP8fjDMjbNptBmao7aazDoZfF/6dQxzioFPzAWBhZ6lVitRrKr6UwqumoSDqP7nbUFqQxEys7kYm4tEOTCgO45+s0GS/56wjM4DiL9weU8PO/3pINTB36FSyHxMUeugZ1ITG9//LXn5gMLvSJJ5//vsI73+lsOcYiruUGhaGbYXdgXL8jRIjbuAA8EKcQ= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: a4c57f22-0cc6-4ce8-875c-08db98ee5d6f X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Aug 2023 15:36:14.2213 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: NxrT4AJxXwMg+99cnpwST+v0hDzH7YCIzMQaKuDMox334bFbjMqZojzjVRdyRpEqi/LVcZrt9st/GXSRLX169Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8PR04MB7161 X-Spam-Status: No, score=-1.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO,SPF_HELO_PASS, T_SPF_PERMERROR,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org Introduce helper function dw_pcie_get_ltssm() to retrieve SMLH_LTSS_STATE. Add callback .pme_turn_off and .exit_from_l2 for platform specific PME handling. Add common dw_pcie_suspend(resume)_noirq() API to avoid duplicated code in dwc pci host controller platform driver. Typical L2 entry workflow/dw_pcie_suspend_noirq() 1. Transmit PME turn off signal to PCI devices and wait for PME_To_Ack. 2. Await link entering L2_IDLE state. Typical L2 exit workflow/dw_pcie_resume_noirq() 1. Issue exit from L2 command. 2. Reinitialize PCI host. 3. Wait for link to become active. Acked-by: Manivannan Sadhasivam Signed-off-by: Frank Li --- .../pci/controller/dwc/pcie-designware-host.c | 76 +++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 29 +++++++ 2 files changed, 105 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 9952057c8819c..cdbff11a7d00e 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -8,6 +8,7 @@ * Author: Jingoo Han */ +#include #include #include #include @@ -16,6 +17,7 @@ #include #include +#include "../../pci.h" #include "pcie-designware.h" static struct pci_ops dw_pcie_ops; @@ -807,3 +809,77 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) return 0; } EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); + +int dw_pcie_suspend_noirq(struct dw_pcie *pci) +{ + u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + u32 val; + int ret; + + /* + * If L1SS is supported, then do not put the link into L2 as some + * devices such as NVMe expect low resume latency. + */ + if (dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL) & PCI_EXP_LNKCTL_ASPM_L1) + return 0; + + if (dw_pcie_get_ltssm(pci) <= DW_PCIE_LTSSM_DETECT_ACT) + return 0; + + if (!pci->pp.ops->pme_turn_off) + return 0; + + pci->pp.ops->pme_turn_off(&pci->pp); + + ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE, + PCIE_PME_TO_L2_TIMEOUT_US/10, + PCIE_PME_TO_L2_TIMEOUT_US, false, pci); + if (ret) { + dev_err(pci->dev, "Timeout waiting for L2 entry! LTSSM: 0x%x\n", val); + return ret; + } + + if (pci->pp.ops->host_deinit) + pci->pp.ops->host_deinit(&pci->pp); + + pci->suspended = true; + + return ret; +} +EXPORT_SYMBOL_GPL(dw_pcie_suspend_noirq); + +int dw_pcie_resume_noirq(struct dw_pcie *pci) +{ + int ret; + + if (!pci->suspended) + return 0; + + pci->suspended = false; + + if (!pci->pp.ops->exit_from_l2) + return 0; + + pci->pp.ops->exit_from_l2(&pci->pp); + + if (pci->pp.ops->host_init) { + ret = pci->pp.ops->host_init(&pci->pp); + if (ret) { + dev_err(pci->dev, "Host init failed: %d\n", ret); + return ret; + } + } + + dw_pcie_setup_rc(&pci->pp); + + ret = dw_pcie_start_link(pci); + if (ret) + return ret; + + ret = dw_pcie_wait_for_link(pci); + if (ret) + return ret; + + return ret; +} +EXPORT_SYMBOL_GPL(dw_pcie_resume_noirq); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 79713ce075cc1..629bccfa92ddd 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -288,10 +288,22 @@ enum dw_pcie_core_rst { DW_PCIE_NUM_CORE_RSTS }; +enum dw_pcie_ltssm { + /* Need to align with PCIE_PORT_DEBUG0 bits 0:5 */ + DW_PCIE_LTSSM_DETECT_QUIET = 0x0, + DW_PCIE_LTSSM_DETECT_ACT = 0x1, + DW_PCIE_LTSSM_L0 = 0x11, + DW_PCIE_LTSSM_L2_IDLE = 0x15, + + DW_PCIE_LTSSM_UNKNOWN = 0xFFFFFFFF, +}; + struct dw_pcie_host_ops { int (*host_init)(struct dw_pcie_rp *pp); void (*host_deinit)(struct dw_pcie_rp *pp); int (*msi_host_init)(struct dw_pcie_rp *pp); + void (*pme_turn_off)(struct dw_pcie_rp *pp); + void (*exit_from_l2)(struct dw_pcie_rp *pp); }; struct dw_pcie_rp { @@ -364,6 +376,7 @@ struct dw_pcie_ops { void (*write_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg, size_t size, u32 val); int (*link_up)(struct dw_pcie *pcie); + enum dw_pcie_ltssm (*get_ltssm)(struct dw_pcie *pcie); int (*start_link)(struct dw_pcie *pcie); void (*stop_link)(struct dw_pcie *pcie); }; @@ -393,6 +406,7 @@ struct dw_pcie { struct reset_control_bulk_data app_rsts[DW_PCIE_NUM_APP_RSTS]; struct reset_control_bulk_data core_rsts[DW_PCIE_NUM_CORE_RSTS]; struct gpio_desc *pe_rst; + bool suspended; }; #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp) @@ -430,6 +444,9 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci); int dw_pcie_edma_detect(struct dw_pcie *pci); void dw_pcie_edma_remove(struct dw_pcie *pci); +int dw_pcie_suspend_noirq(struct dw_pcie *pci); +int dw_pcie_resume_noirq(struct dw_pcie *pci); + static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val) { dw_pcie_write_dbi(pci, reg, 0x4, val); @@ -501,6 +518,18 @@ static inline void dw_pcie_stop_link(struct dw_pcie *pci) pci->ops->stop_link(pci); } +static inline enum dw_pcie_ltssm dw_pcie_get_ltssm(struct dw_pcie *pci) +{ + u32 val; + + if (pci->ops && pci->ops->get_ltssm) + return pci->ops->get_ltssm(pci); + + val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0); + + return (enum dw_pcie_ltssm)FIELD_GET(PORT_LOGIC_LTSSM_STATE_MASK, val); +} + #ifdef CONFIG_PCIE_DW_HOST irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp); int dw_pcie_setup_rc(struct dw_pcie_rp *pp);