| Message ID | 20230619014218.1970846-1-vidyas@nvidia.com |
|---|---|
| State | New |
| Headers | show |
| Series | [V2] Revert "PCI: tegra194: Enable support for 256 Byte payload" | expand |
Hi Vidya,
kernel test robot noticed the following build errors:
[auto build test ERROR on pci/next]
[also build test ERROR on pci/for-linus linus/master v6.4-rc7 next-20230616]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Vidya-Sagar/Revert-PCI-tegra194-Enable-support-for-256-Byte-payload/20230619-094403
base: https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link: https://lore.kernel.org/r/20230619014218.1970846-1-vidyas%40nvidia.com
patch subject: [PATCH V2] Revert "PCI: tegra194: Enable support for 256 Byte payload"
config: arm64-defconfig (https://download.01.org/0day-ci/archive/20230619/202306191113.M2RDKBvQ-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 12.3.0
reproduce: (https://download.01.org/0day-ci/archive/20230619/202306191113.M2RDKBvQ-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202306191113.M2RDKBvQ-lkp@intel.com/
All errors (new ones prefixed by >>):
drivers/pci/controller/dwc/pcie-tegra194.c: In function 'tegra_pcie_dw_host_init':
>> drivers/pci/controller/dwc/pcie-tegra194.c:906:17: error: 'val_16' undeclared (first use in this function)
906 | val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
| ^~~~~~
drivers/pci/controller/dwc/pcie-tegra194.c:906:17: note: each undeclared identifier is reported only once for each function it appears in
drivers/pci/controller/dwc/pcie-tegra194.c: In function 'pex_ep_event_pex_rst_deassert':
drivers/pci/controller/dwc/pcie-tegra194.c:1865:17: error: 'val_16' undeclared (first use in this function)
1865 | val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
| ^~~~~~
vim +/val_16 +906 drivers/pci/controller/dwc/pcie-tegra194.c
56e15a238d9278 Vidya Sagar 2019-08-13 867
64451ac83fe6ab Bjorn Helgaas 2022-08-04 868 static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp)
56e15a238d9278 Vidya Sagar 2019-08-13 869 {
56e15a238d9278 Vidya Sagar 2019-08-13 870 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
f1ab409d578752 Vidya Sagar 2022-07-21 871 struct tegra_pcie_dw *pcie = to_tegra_pcie(pci);
56e15a238d9278 Vidya Sagar 2019-08-13 872 u32 val;
56e15a238d9278 Vidya Sagar 2019-08-13 873
275e88b06a277c Rob Herring 2020-12-18 874 pp->bridge->ops = &tegra_pci_ops;
275e88b06a277c Rob Herring 2020-12-18 875
369b868f4a2ef8 Vidya Sagar 2020-11-26 876 if (!pcie->pcie_cap_base)
369b868f4a2ef8 Vidya Sagar 2020-11-26 877 pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci,
369b868f4a2ef8 Vidya Sagar 2020-11-26 878 PCI_CAP_ID_EXP);
369b868f4a2ef8 Vidya Sagar 2020-11-26 879
56e15a238d9278 Vidya Sagar 2019-08-13 880 val = dw_pcie_readl_dbi(pci, PCI_IO_BASE);
56e15a238d9278 Vidya Sagar 2019-08-13 881 val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8);
56e15a238d9278 Vidya Sagar 2019-08-13 882 dw_pcie_writel_dbi(pci, PCI_IO_BASE, val);
56e15a238d9278 Vidya Sagar 2019-08-13 883
56e15a238d9278 Vidya Sagar 2019-08-13 884 val = dw_pcie_readl_dbi(pci, PCI_PREF_MEMORY_BASE);
56e15a238d9278 Vidya Sagar 2019-08-13 885 val |= CFG_PREF_MEM_LIMIT_BASE_MEM_DECODE;
56e15a238d9278 Vidya Sagar 2019-08-13 886 val |= CFG_PREF_MEM_LIMIT_BASE_MEM_LIMIT_DECODE;
56e15a238d9278 Vidya Sagar 2019-08-13 887 dw_pcie_writel_dbi(pci, PCI_PREF_MEMORY_BASE, val);
56e15a238d9278 Vidya Sagar 2019-08-13 888
56e15a238d9278 Vidya Sagar 2019-08-13 889 dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);
56e15a238d9278 Vidya Sagar 2019-08-13 890
56e15a238d9278 Vidya Sagar 2019-08-13 891 /* Enable as 0xFFFF0001 response for CRS */
56e15a238d9278 Vidya Sagar 2019-08-13 892 val = dw_pcie_readl_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT);
56e15a238d9278 Vidya Sagar 2019-08-13 893 val &= ~(AMBA_ERROR_RESPONSE_CRS_MASK << AMBA_ERROR_RESPONSE_CRS_SHIFT);
56e15a238d9278 Vidya Sagar 2019-08-13 894 val |= (AMBA_ERROR_RESPONSE_CRS_OKAY_FFFF0001 <<
56e15a238d9278 Vidya Sagar 2019-08-13 895 AMBA_ERROR_RESPONSE_CRS_SHIFT);
56e15a238d9278 Vidya Sagar 2019-08-13 896 dw_pcie_writel_dbi(pci, PORT_LOGIC_AMBA_ERROR_RESPONSE_DEFAULT, val);
56e15a238d9278 Vidya Sagar 2019-08-13 897
56e15a238d9278 Vidya Sagar 2019-08-13 898 /* Configure Max lane width from DT */
56e15a238d9278 Vidya Sagar 2019-08-13 899 val = dw_pcie_readl_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP);
56e15a238d9278 Vidya Sagar 2019-08-13 900 val &= ~PCI_EXP_LNKCAP_MLW;
56e15a238d9278 Vidya Sagar 2019-08-13 901 val |= (pcie->num_lanes << PCI_EXP_LNKSTA_NLW_SHIFT);
56e15a238d9278 Vidya Sagar 2019-08-13 902 dw_pcie_writel_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKCAP, val);
56e15a238d9278 Vidya Sagar 2019-08-13 903
a54e190737181c Vidya Sagar 2022-07-21 904 /* Clear Slot Clock Configuration bit if SRNS configuration */
a54e190737181c Vidya Sagar 2022-07-21 905 if (pcie->enable_srns) {
a54e190737181c Vidya Sagar 2022-07-21 @906 val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base +
a54e190737181c Vidya Sagar 2022-07-21 907 PCI_EXP_LNKSTA);
a54e190737181c Vidya Sagar 2022-07-21 908 val_16 &= ~PCI_EXP_LNKSTA_SLC;
a54e190737181c Vidya Sagar 2022-07-21 909 dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA,
a54e190737181c Vidya Sagar 2022-07-21 910 val_16);
a54e190737181c Vidya Sagar 2022-07-21 911 }
a54e190737181c Vidya Sagar 2022-07-21 912
56e15a238d9278 Vidya Sagar 2019-08-13 913 config_gen3_gen4_eq_presets(pcie);
56e15a238d9278 Vidya Sagar 2019-08-13 914
56e15a238d9278 Vidya Sagar 2019-08-13 915 init_host_aspm(pcie);
56e15a238d9278 Vidya Sagar 2019-08-13 916
6b6fafc1abc7c0 Vidya Sagar 2020-12-03 917 /* Disable ASPM-L1SS advertisement if there is no CLKREQ routing */
6b6fafc1abc7c0 Vidya Sagar 2020-12-03 918 if (!pcie->supports_clkreq) {
6b6fafc1abc7c0 Vidya Sagar 2020-12-03 919 disable_aspm_l11(pcie);
6b6fafc1abc7c0 Vidya Sagar 2020-12-03 920 disable_aspm_l12(pcie);
6b6fafc1abc7c0 Vidya Sagar 2020-12-03 921 }
6b6fafc1abc7c0 Vidya Sagar 2020-12-03 922
a54e190737181c Vidya Sagar 2022-07-21 923 if (!pcie->of_data->has_l1ss_exit_fix) {
56e15a238d9278 Vidya Sagar 2019-08-13 924 val = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
56e15a238d9278 Vidya Sagar 2019-08-13 925 val &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
56e15a238d9278 Vidya Sagar 2019-08-13 926 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, val);
a54e190737181c Vidya Sagar 2022-07-21 927 }
56e15a238d9278 Vidya Sagar 2019-08-13 928
56e15a238d9278 Vidya Sagar 2019-08-13 929 if (pcie->update_fc_fixup) {
56e15a238d9278 Vidya Sagar 2019-08-13 930 val = dw_pcie_readl_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF);
56e15a238d9278 Vidya Sagar 2019-08-13 931 val |= 0x1 << CFG_TIMER_CTRL_ACK_NAK_SHIFT;
56e15a238d9278 Vidya Sagar 2019-08-13 932 dw_pcie_writel_dbi(pci, CFG_TIMER_CTRL_MAX_FUNC_NUM_OFF, val);
56e15a238d9278 Vidya Sagar 2019-08-13 933 }
56e15a238d9278 Vidya Sagar 2019-08-13 934
56e15a238d9278 Vidya Sagar 2019-08-13 935 clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ);
56e15a238d9278 Vidya Sagar 2019-08-13 936
275e88b06a277c Rob Herring 2020-12-18 937 return 0;
275e88b06a277c Rob Herring 2020-12-18 938 }
275e88b06a277c Rob Herring 2020-12-18 939
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 4fdadc7b045f..877d81b13334 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -892,7 +892,6 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp) struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct tegra_pcie_dw *pcie = to_tegra_pcie(pci); u32 val; - u16 val_16; pp->bridge->ops = &tegra_pci_ops; @@ -900,11 +899,6 @@ static int tegra_pcie_dw_host_init(struct dw_pcie_rp *pp) pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, PCI_CAP_ID_EXP); - val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL); - val_16 &= ~PCI_EXP_DEVCTL_PAYLOAD; - val_16 |= PCI_EXP_DEVCTL_PAYLOAD_256B; - dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16); - val = dw_pcie_readl_dbi(pci, PCI_IO_BASE); val &= ~(IO_BASE_IO_DECODE | IO_BASE_IO_DECODE_BIT8); dw_pcie_writel_dbi(pci, PCI_IO_BASE, val); @@ -1756,7 +1750,6 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) struct device *dev = pcie->dev; u32 val; int ret; - u16 val_16; if (pcie->ep_state == EP_STATE_ENABLED) return; @@ -1887,11 +1880,6 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) pcie->pcie_cap_base = dw_pcie_find_capability(&pcie->pci, PCI_CAP_ID_EXP); - val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL); - val_16 &= ~PCI_EXP_DEVCTL_PAYLOAD; - val_16 |= PCI_EXP_DEVCTL_PAYLOAD_256B; - dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_DEVCTL, val_16); - /* Clear Slot Clock Configuration bit if SRNS configuration */ if (pcie->enable_srns) { val_16 = dw_pcie_readw_dbi(pci, pcie->pcie_cap_base + @@ -1900,7 +1888,6 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie) dw_pcie_writew_dbi(pci, pcie->pcie_cap_base + PCI_EXP_LNKSTA, val_16); } - clk_set_rate(pcie->core_clk, GEN4_CORE_CLK_FREQ); val = (ep->msi_mem_phys & MSIX_ADDR_MATCH_LOW_OFF_MASK);
This reverts commit 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte payload"). Consider a PCIe hierarchy with a PCIe switch and a device connected downstream of the switch that has support for MPS which is the minimum in the hierarchy, and root port programmed with an MPS in its DevCtl register that is greater than the minimum. In this scenario, the default bus configuration of the kernel i.e. "PCIE_BUS_DEFAULT" doesn't configure the MPS settings in the hierarchy correctly resulting in the device with support for minimum MPS in the hierarchy receiving the TLPs of size more than that. Although this can be addressed by appending "pci=pcie_bus_safe" to the kernel command line, it doesn't seem to be a good idea to always have this commandline argument even for the basic functionality to work. Reverting commit 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte payload") avoids this requirement and ensures that the basic functionality of the devices irrespective of the hierarchy and the MPS of the devices in the hierarchy. To reap the benefits of having support for higher MPS, optionally, one can always append the kernel command line with "pci=pcie_bus_perf". Fixes: 4fb8e46c1bc4 ("PCI: tegra194: Enable support for 256 Byte payload") Signed-off-by: Vidya Sagar <vidyas@nvidia.com> --- V2: * Addressed review comments from Bjorn drivers/pci/controller/dwc/pcie-tegra194.c | 13 ------------- 1 file changed, 13 deletions(-)