| Message ID | 20230531095713.293229-1-ben.dooks@codethink.co.uk |
|---|---|
| State | New |
| Headers | show |
| Series | [PATCHv2] pci: add PCI_EXT_CAP_ID_PL_32GT define | expand |
On Wed, May 31, 2023 at 10:57:13AM +0100, Ben Dooks wrote: > From: Ben Dooks <ben.dooks@sifive.com> > > Add the define for PCI_EXT_CAP_ID_PL_32GT for drivers that > will want this whilst doing Gen5/Gen6 accesses. > > Signed-off-by: Ben Dooks <ben.dooks@sifive.com> > Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> I applied this to pci/enumeration for v6.5, thanks. But I'm very curious about where you expect this to be used. > -- > v2: > - fixed tabs > --- > include/uapi/linux/pci_regs.h | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h > index dc2000e0fe3a..e5f558d96493 100644 > --- a/include/uapi/linux/pci_regs.h > +++ b/include/uapi/linux/pci_regs.h > @@ -738,6 +738,7 @@ > #define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ > #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ > #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ > +#define PCI_EXT_CAP_ID_PL_32GT 0x2A /* Physical Layer 32.0 GT/s */ > #define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */ > #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_DOE > > -- > 2.39.2 >
On 31/05/2023 22:37, Bjorn Helgaas wrote: > On Wed, May 31, 2023 at 10:57:13AM +0100, Ben Dooks wrote: >> From: Ben Dooks <ben.dooks@sifive.com> >> >> Add the define for PCI_EXT_CAP_ID_PL_32GT for drivers that >> will want this whilst doing Gen5/Gen6 accesses. >> >> Signed-off-by: Ben Dooks <ben.dooks@sifive.com> >> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> > > I applied this to pci/enumeration for v6.5, thanks. > > But I'm very curious about where you expect this to be used. We have an upcoming driver that has gen5 phy and config requirements.
On Fri, Jun 02, 2023 at 02:08:45PM +0100, Ben Dooks wrote: > On 31/05/2023 22:37, Bjorn Helgaas wrote: > > On Wed, May 31, 2023 at 10:57:13AM +0100, Ben Dooks wrote: > > > From: Ben Dooks <ben.dooks@sifive.com> > > > > > > Add the define for PCI_EXT_CAP_ID_PL_32GT for drivers that > > > will want this whilst doing Gen5/Gen6 accesses. > > > > > > Signed-off-by: Ben Dooks <ben.dooks@sifive.com> > > > Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> > > > > I applied this to pci/enumeration for v6.5, thanks. > > > > But I'm very curious about where you expect this to be used. > > We have an upcoming driver that has gen5 phy and config requirements. I guess a better question would have been whether PCI_EXT_CAP_ID_PL_32GT is best used in individual drivers or in the PCI core. Since it's in the PCIe base spec and doesn't look like it should be device-specific, it might be a candidate for supporting in the PCI core somehow so it doesn't get reimplemented in several places. Bjorn
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index dc2000e0fe3a..e5f558d96493 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -738,6 +738,7 @@ #define PCI_EXT_CAP_ID_DVSEC 0x23 /* Designated Vendor-Specific */ #define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ #define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ +#define PCI_EXT_CAP_ID_PL_32GT 0x2A /* Physical Layer 32.0 GT/s */ #define PCI_EXT_CAP_ID_DOE 0x2E /* Data Object Exchange */ #define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_DOE