diff mbox series

pci: add PCI_EXT_CAP_ID_PL_32GT define

Message ID 20230531095545.293063-1-ben.dooks@codethink.co.uk
State New
Headers show
Series pci: add PCI_EXT_CAP_ID_PL_32GT define | expand

Commit Message

Ben Dooks May 31, 2023, 9:55 a.m. UTC
From: Ben Dooks <ben.dooks@sifive.com>

Add the define for PCI_EXT_CAP_ID_PL_32GT for drivers that
will want this whilst doing Gen5/Gen6 accesses.

Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
 include/uapi/linux/pci_regs.h | 1 +
 1 file changed, 1 insertion(+)

Comments

Ben Dooks May 31, 2023, 9:57 a.m. UTC | #1
On 31/05/2023 10:55, Ben Dooks wrote:
> From: Ben Dooks <ben.dooks@sifive.com>
> 
> Add the define for PCI_EXT_CAP_ID_PL_32GT for drivers that
> will want this whilst doing Gen5/Gen6 accesses.
> 
> Signed-off-by: Ben Dooks <ben.dooks@sifive.com>
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> ---
>   include/uapi/linux/pci_regs.h | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
> index dc2000e0fe3a..e5f558d96493 100644
> --- a/include/uapi/linux/pci_regs.h
> +++ b/include/uapi/linux/pci_regs.h
> @@ -738,6 +738,7 @@
>   #define PCI_EXT_CAP_ID_DVSEC	0x23	/* Designated Vendor-Specific */
>   #define PCI_EXT_CAP_ID_DLF	0x25	/* Data Link Feature */
>   #define PCI_EXT_CAP_ID_PL_16GT	0x26	/* Physical Layer 16.0 GT/s */
> +#define PCI_EXT_CAP_ID_PL_32GT  0x2A    /* Physical Layer 32.0 GT/s */
>   #define PCI_EXT_CAP_ID_DOE	0x2E	/* Data Object Exchange */
>   #define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_DOE

Just noticed this isn't tab indented, so fixed and sent a v2.
diff mbox series

Patch

diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index dc2000e0fe3a..e5f558d96493 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -738,6 +738,7 @@ 
 #define PCI_EXT_CAP_ID_DVSEC	0x23	/* Designated Vendor-Specific */
 #define PCI_EXT_CAP_ID_DLF	0x25	/* Data Link Feature */
 #define PCI_EXT_CAP_ID_PL_16GT	0x26	/* Physical Layer 16.0 GT/s */
+#define PCI_EXT_CAP_ID_PL_32GT  0x2A    /* Physical Layer 32.0 GT/s */
 #define PCI_EXT_CAP_ID_DOE	0x2E	/* Data Object Exchange */
 #define PCI_EXT_CAP_ID_MAX	PCI_EXT_CAP_ID_DOE