| Message ID | 20230112072111.20063-1-vidyas@nvidia.com |
|---|---|
| State | New |
| Headers | show |
| Series | [V2] PCI/AER: Configure ECRC only AER is native | expand |
On Thu, Jan 12, 2023 at 12:51:11PM +0530, Vidya Sagar wrote: > As the ECRC configuration bits are part of AER registers, configure > ECRC only if AER is natively owned by the kernel. > > Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Applied to pci/aer for v6.3, thanks! > --- > v2: > * Updated kernel-parameters.txt document based on Bjorn's suggestion > > Documentation/admin-guide/kernel-parameters.txt | 4 +++- > drivers/pci/pcie/aer.c | 3 +++ > 2 files changed, 6 insertions(+), 1 deletion(-) > > diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt > index 426fa892d311..8f85a1230525 100644 > --- a/Documentation/admin-guide/kernel-parameters.txt > +++ b/Documentation/admin-guide/kernel-parameters.txt > @@ -4242,7 +4242,9 @@ > specified, e.g., 12@pci:8086:9c22:103c:198f > for 4096-byte alignment. > ecrc= Enable/disable PCIe ECRC (transaction layer > - end-to-end CRC checking). > + end-to-end CRC checking). Only effective if > + OS has native AER control (either granted by > + ACPI _OSC or forced via "pcie_ports=native") > bios: Use BIOS/firmware settings. This is the > the default. > off: Turn ECRC off > diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c > index e2d8a74f83c3..730b47bdcdef 100644 > --- a/drivers/pci/pcie/aer.c > +++ b/drivers/pci/pcie/aer.c > @@ -184,6 +184,9 @@ static int disable_ecrc_checking(struct pci_dev *dev) > */ > void pcie_set_ecrc_checking(struct pci_dev *dev) > { > + if (!pcie_aer_is_native(dev)) > + return; > + > switch (ecrc_policy) { > case ECRC_POLICY_DEFAULT: > return; > -- > 2.17.1 >
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 426fa892d311..8f85a1230525 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -4242,7 +4242,9 @@ specified, e.g., 12@pci:8086:9c22:103c:198f for 4096-byte alignment. ecrc= Enable/disable PCIe ECRC (transaction layer - end-to-end CRC checking). + end-to-end CRC checking). Only effective if + OS has native AER control (either granted by + ACPI _OSC or forced via "pcie_ports=native") bios: Use BIOS/firmware settings. This is the the default. off: Turn ECRC off diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index e2d8a74f83c3..730b47bdcdef 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -184,6 +184,9 @@ static int disable_ecrc_checking(struct pci_dev *dev) */ void pcie_set_ecrc_checking(struct pci_dev *dev) { + if (!pcie_aer_is_native(dev)) + return; + switch (ecrc_policy) { case ECRC_POLICY_DEFAULT: return;
As the ECRC configuration bits are part of AER registers, configure ECRC only if AER is natively owned by the kernel. Signed-off-by: Vidya Sagar <vidyas@nvidia.com> --- v2: * Updated kernel-parameters.txt document based on Bjorn's suggestion Documentation/admin-guide/kernel-parameters.txt | 4 +++- drivers/pci/pcie/aer.c | 3 +++ 2 files changed, 6 insertions(+), 1 deletion(-)